Lateral soi semiconductor device

• US 20070120187A1
• Filed: 05/13/2003
• Published: 05/31/2007
• Est. Priority Date: 05/13/2003
• Status: Active Grant

• Current Assignee: Cambridge Microelectronics Limited
• Original Assignee: Cambridge Semiconductor Limited (Power Integrations Incorporated)
• Inventors: Udrea, Florin, Garner, David
• Granted Patent: US 7,531,875 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/8086 Thin film JFET's
• CPC Class Codes: H01L 29/861 Diodes

Abstract

This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity type; a second region of a second conductivity type laterally spaced apart from said first region; and a drift region extending in a lateral direction between said first region and said second region; and wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered to narrow towards said first region.

Claims

1. A lateral semiconductor-on-insulator device comprising:

a semiconductor substrate′

an insulating layer on said semiconductor substrate; and

a lateral semiconductor device on said insulator;

said lateral semiconductor device having;

a first region of a first conductivity type;

a second region of a second conductivity type laterally spaced apart from said first region; and

a drift region extending in a lateral direction between said first region and said second region; and

wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered to narrow towards said first region.

2. A lateral semiconductor-on-insulator device as claimed in claim 1 wherein said drift region comprises interdigitated first and second zones.

3. A lateral semiconductor-on-insulator device as claimed in claims 1 wherein a said second zone is tapered to narrow towards said second region.

4. A lateral semiconductor-on-insulator device as claimed in claim 3 wherein said first and second zones are tapered in a width perpendicular to said lateral direction.

9. A lateral semiconductor-on-insulator device as claimed in claim 1 wherein said first zones are substantially uniformly doped.

10. A lateral semiconductor-on-insulator device as claimed in claim 1 wherein said semiconductor comprises silicon, wherein said insulating layer comprises a buried oxide layer, and wherein a said second zone comprises an oxide zone.

11. A lateral semiconductor-on-insulator device as claimed in claim 1 any claim wherein said semiconductor device comprises a MOS device, wherein said first region comprises a body region of said MOS device, said MOS device further comprising a third region of said second conductivity type adjacent said body region, and a control electrode disposed over at least a portion of said body region, and a control electrode disposed over at least a portion of said body region and over a portion of said later drift region and insulated from said body region and from said drift region by an insulating region.

12. A later semiconductor-on-insulator device as claimed in claim 11 wherein said lateral MOS device comprises a lateral MOSFET, wherein said second region comprises a drain region of said MOSFET, wherein said third region comprises a source region of said MOSFET, and wherein said control electrode comprises a gate of said MOSFET.

13. A lateral semiconductor-on-insulator device as claimed in claim 11 wherein said lateral MOS device comprises a lateral insulated gate bipolar transistor (IGBT), said lateral IGBT further comprising a fourth region of said first conductivity type adjacent said third region.

14. A lateral semiconductor-on-insulator device as claimed in claim 1 wherein said lateral semiconductor device comprises a junction field effect transistor (JFET).

15. A lateral semiconductor-on-insulator device as claimed in claim 1 wherein said first conductivity type is p-type and said second conductivity type is n-type.

5. A lateral semiconductor-on-insulator device comprising:

a semiconductor substrate;

an insulating layer on said semiconductor substrate; and

a lateral semiconductor device on said insulator;

said lateral semiconductor device having;

a first region of a first conductivity type;

a second region of a second conductivity type laterally spaced apart from said first region; and

a drift region extending a lateral direction between said first and said second region; and

wherein said drift region comprises interdigitated first and second zones, said first zones having said second conductivity type, a said second zone being an insulating zone, and wherein a ration of a lateral area of said drift region occupied by a said first zone to a lateral area occupied by a said second zone is less towards said first region than towards said second region.

6. A lateral semiconductor-on-insulator device as claimed in claim 5 wherein each said second zone comprises a finger having a length extending perpendicular to said lateral direction.

7. A lateral semiconductor as claimed in claim 6 having a plurality of said fingers, lengths of said fingers increasing towards said first region.

8. A lateral semiconductor as claimed in claim 7 having a plurality of said fingers, spacings between said fingers reducing towards said first region.

16. A lateral semiconductor-on-insulator device comprising a semiconductor substrate bearing an insulated layer over which a lateral MOS device is formed, the later MOS device comprising first and second semiconductor regions of opposing conductivity types linked by a lateral drift semiconductor region, said drift region comprising a plurality of zones, undoped zones alternating with doped zones, said doped zones joining said first and second regions and having an overall area which reduces from one of said first and second regions to the other of said first and second regions, whereby said drift region has a varying charge in a lateral direction between said first and second regions.

17. A lateral semiconductor-on-insulator device as claimed in claim 16 wherein said doped zones have a conductivity type matching that of said second region, and wherein said drift region charge reduces away from said second region.

18. A lateral semiconductor-on-insulator device as claimed in claim 16 wherein said undoped zones comprise oxide zones.

19. A lateral semiconductor-on-insulator device as claimed in claim 16 wherein said lateral MOS device comprises a lateral MOSFET.

20. A lateral semiconductor-on-insulator device as claimed in claim 16 wherein said lateral MOS device comprises a lateral IGBT.

21. A lateral semiconductor-on-insulator device as claimed in claim 16 wherein said lateral MOS device comprises a lateral JFET.

22. A silicon-on-insulator lateral MOS device having a drift region comprising a plurality of doped zones, said doped zones being interleaved with insulating zones.

23. A silicon-on-insulator lateral MOS device as claimed in claim 22 wherein said doped zones are tapered.

24. A silicon-on-insulator lateral MOS device as claimed in claim 23 wherein said insulating zones comprise tapered oxide zones, oppositely tapered to said doped zones.

25. A lateral semiconductor-on-insulator device comprising:

a semiconductor substrate;

an insulating layer on said semiconductor substrate; and

a lateral semiconductor device on said insulator;

said lateral semiconductor device having;

a first region of a first conductivity type;

a second region of a second conductivity type laterally spaced apart from said first region; and

a drift region extending in a lateral direction between said first region and said second region; and

wherein said drift region comprises at least one doped zone having said second conductivity type, said doped zone having a dimension which reduces towards said first region.

26. A lateral semiconductor-on-insulator device as claimed in claim 25 wherein said drift region further comprises at least one undoped zone.

27. A lateral semiconductor-on-insulator device as claimed in claim 25 wherein said doped zone has a width perpendicular to said lateral direction which reduces towards said first region.

28. A lateral semiconductor-on-insulator device as claimed in claim 26 wherein said undoped zone further comprises an insulating zone adjacent said doped zone.

29. A later semiconductor-on-insulator device as claimed in claim 26 wherein said undoped zone reduces in width towards said second region.