Semiconductor device and a method of manufacturing the same
First Claim
1. A semiconductor device including a trench gate type MISFET, comprising:
- a semiconductor substrate having a main surface and a bottom surface opposite to said main surface, said semiconductor substrate having a first conductivity type;
a first semiconductor layer formed on the main surface of the semiconductor substrate, said first semiconductor layer having a top surface apart from the semiconductor substrate, said first semiconductor layer having the first conductivity type, and said first semiconductor layer acting as a drain region of the MISFET;
a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 μ
m;
a gate insulating film of the MISFET formed on an inner surface of the trench;
a gate electrode of the MISFET formed on the gate insulating film in the trench;
a channel forming region of the MISFET formed in the first semiconductor layer, said channel forming region being in contact with the trench, said bottom of the trench being positioned below a bottom of the channel forming region, and said channel forming region having a second conductivity type opposite to the first conductivity type;
a source region of the MISFET formed over the channel forming region in the first semiconductor layer;
said source region being in contact with the trench, and said source region having the first conductivity type; and
a punch through stopper region formed between the source region and channel forming region in the first semiconductor layer, said punch through stopper region having the second conductivity type, and said punch through stopper region having a higher impurity concentration than the channel forming region.
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Accused Products
Abstract
A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p− type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p− type semiconductor region is formed under a n+ type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.
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Citations
3 Claims
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1. A semiconductor device including a trench gate type MISFET, comprising:
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a semiconductor substrate having a main surface and a bottom surface opposite to said main surface, said semiconductor substrate having a first conductivity type;
a first semiconductor layer formed on the main surface of the semiconductor substrate, said first semiconductor layer having a top surface apart from the semiconductor substrate, said first semiconductor layer having the first conductivity type, and said first semiconductor layer acting as a drain region of the MISFET;
a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 μ
m;
a gate insulating film of the MISFET formed on an inner surface of the trench;
a gate electrode of the MISFET formed on the gate insulating film in the trench;
a channel forming region of the MISFET formed in the first semiconductor layer, said channel forming region being in contact with the trench, said bottom of the trench being positioned below a bottom of the channel forming region, and said channel forming region having a second conductivity type opposite to the first conductivity type;
a source region of the MISFET formed over the channel forming region in the first semiconductor layer;
said source region being in contact with the trench, and said source region having the first conductivity type; and
a punch through stopper region formed between the source region and channel forming region in the first semiconductor layer, said punch through stopper region having the second conductivity type, and said punch through stopper region having a higher impurity concentration than the channel forming region. - View Dependent Claims (2, 3)
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Specification