Semiconductor chip having island dispersion structure and method for manufacturing the same

• US 20070120255A1
• Filed: 11/15/2006
• Published: 05/31/2007
• Est. Priority Date: 11/30/2005
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Hitachi, Ltd., Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Aoki, Shigeru, Oyu, Kiyonori
• Granted Patent: US 7,911,058 B2
• Time in Patent Office: Days
• US Class Current: 257/750
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 23/26 including materials for absorbing or reacting with moisture or other undesired substances , e.g. getters
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate, the porous silicon domain layer being provided in a main surface region on a back surface which is the other surface of the semiconductor silicon substrate, and the porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon substrate.

Claims

1. A semiconductor chip including a semiconductor silicon substrate having a semiconductor device layer and a porous silicon domain layer,

said semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate,

said porous silicon domain layer being provided in a main surface region on a back surface which is another surface of the semiconductor silicon substrate, and

said porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon substrate.

2. The semiconductor chip of claim 1, wherein the porous silicon domains appearing on the back surface of the semiconductor silicon substrate in said porous silicon domain layer have an average diameter ranging from 0.2 to 800 μ

m provided that a shape of each of the porous silicon domains is replaced with a circle of identical area.

3. The semiconductor chip of claim 1, wherein a total area of the porous silicon domains appearing on the back surface region of the semiconductor silicon substrate in said porous silicon domain layer ranges from 10% to 90% of an area of the back surface.

7. The semiconductor chip of claim 1, further comprising a porous silicon layer on the back surface.

16. A semiconductor device including the semiconductor chip of claim 1.

18. A semiconductor device including the semiconductor chip of claim 7.

4. A semiconductor chip including a semiconductor silicon substrate having a semiconductor device layer and a dimple layer,

said semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate,

said dimple layer being provided in a main surface region on a back surface which is another surface of the semiconductor silicon substrate, and

said dimple layer having dimples dispersed like islands in the back surface of the semiconductor silicon substrate.

5. The semiconductor chip of claim 4, wherein the dimples appearing have an average diameter ranging from 0.2 to 800 μ

m provided that a shape of each of the dimples is replaced with a circle of identical area.

6. The semiconductor chip of claim 4, wherein a total area of the dimples ranges from 10% to 90% of an area of the back surface.

8. The semiconductor chip of claim 4, further comprising a porous silicon layer on the back surface.

17. A semiconductor device including the semiconductor chip of claim 4.

19. A semiconductor device including the semiconductor chip of claim 8.

9. A method for manufacturing a semiconductor chip comprising the steps of:

(1) forming a semiconductor device layer in a main surface region on one surface of a semiconductor silicon wafer;

(2) grinding a back surface which is another surface of the semiconductor silicon wafer up to a predetermined thickness;

(3) forming a porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon wafer; and

(4) dicing a worked semiconductor wafer obtained through the steps (1) to (3), and

the step (3) including bringing a mixed vapor of hydrofluoric acid and nitric acid into contact with the back surface of the semiconductor silicon wafer.

10. The method of claim 9, further comprising, between the steps (3) and (4), the step of (5) removing porous silicon domains from the porous silicon domain layer.

11. The method of claim 9, further comprising, between the steps (3) and (4), the step of forming a porous silicon layer on the back surface of the semiconductor silicon wafer.

12. The method of claim 10, further comprising, between the steps (5) and (4), the step of forming a porous silicon layer on the back surface of the semiconductor silicon wafer.

15. A semiconductor chip obtained by the method of claim 9.

20. A semiconductor device including the semiconductor chip of claim 15.

13. A method of manufacturing a semiconductor ship comprising the steps of:

(i) forming a semiconductor device layer in a main surface region on one surface of a semiconductor silicon wafer;

(ii) grinding a back surface which is another surface of the semiconductor silicon wafer up to a predetermined thickness;

(iii) forming a dimple layer having dimples dispersed like islands in the back surface of the semiconductor silicon wafer; and

(iv) dicing a worked semiconductor wafer obtained through the steps (i) to (iii), and

the step (iii) including performing wet etching and/or dry etching on the back surface of the semiconductor silicon wafer.

14. The method of claim 13, further comprising, between the steps (iii) and (iv), the step of forming a porous silicon layer on the back surface of the semiconductor silicon wafer.