METHOD AND APPARATUS FOR FAST LOCKING OF A CLOCK GENERATING CIRCUIT

• US 20070120583A1
• Filed: 11/30/2005
• Published: 05/31/2007
• Est. Priority Date: 11/30/2005
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Chan, Nancy, Senthinathan, Ramesh, Rodionov, Mikhail, Lam, Shirley
• Granted Patent: US 9,455,722 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range

Abstract

In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.

Claims

1. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator comprising:

open feedback loop switch logic responsive to a controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop; and

a dynamic fast lock control signal generator operative to selectively apply a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop.

2. The integrated circuit of claim 1, wherein the dynamic fast lock control signal generator is responsive to a completed controlled change in power supply voltage indication signal and operative to selectively apply the stabilizing control signal to the variable control signal generator.

3. The integrated circuit of claim 1, wherein the dynamic fast lock control signal generator is responsive to a completed controlled change in power supply voltage indication signal and operative to selectively remove the stabilizing control signal from the variable control signal generator.

4. The integrated circuit of claim 1, wherein the open feedback loop switch logic is operative to selectively close the feedback loop in response to the controlled change in power supply voltage indication signal.

5. The integrated circuit of claim 1, wherein the dynamic fast lock control signal generator comprises:

a frequency counter responsive to the generated clock signal and operative to determine the frequency of the generated clock signal;

process corner and stabilizing logic responsive to the frequency of the generated clock signal and operative to determine the process corner of the integrated circuit and is further responsive to a desired power supply voltage and the determined process corner of the integrated circuit, and operative to produce a control signal; and

a resistance divider network responsive to the control signal and operative to produce the stabilizing control signal.

6. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator comprising:

open feedback loop switch logic responsive to a controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop;

a dynamic fast lock control signal generator operative to selectively apply a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop and is responsive to a completed controlled change in power supply voltage indication signal and operative to selectively remove the stabilizing control signal from the variable clock signal generator; and

wherein the open feedback loop switch logic control input is operative to selectively close the feedback loop in response to the controlled change in power supply voltage indication signal.

7. The integrated circuit of claim 6, wherein the open feedback loop switch logic comprises at least one AND gate responsive to the controlled change in power supply voltage signal and operative to selectively control at least one switch of a charge pump, thereby selectively opening the feedback loop and closing the feedback loop, as desired.

8. The integrated circuit of claim 6, wherein the dynamic fast lock control signal generator control input is responsive to a completed controlled change in power supply voltage indication signal and operative to selectively apply the stabilizing control signal to the variable control signal generator.

12. The integrated circuit of claim 8, wherein the clock generating circuit further comprises a loop filter responsive to the charged control signal and operative to generate a phase compensated control signal, and wherein the variable clock signal generator is further responsive to the phase compensated control signal.

9. An integrated circuit having a clock generating circuit with a feedback loop and a variable clock signal generator, the clock generating circuit comprising:

a system phase lock loop having;

a phase frequency detector responsive to a reference clock signal and a feedback clock signal, and operative to produce a phase adjust signal;

a selectively driven charge pump responsive to the phase adjust signal and a controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop and selectively apply a charged control signal to the variable clock signal generator;

wherein the variable clock signal generator is responsive to at least one of the charged control signal, a process corner control signal and a stabilizing control signal, and operative to produce a generated clock signal, wherein the feedback clock signal is based upon the generated clock signal;

a process corner control signal generator responsive to a chip reset indication signal and operative to selectively apply the process corner control signal; and

a dynamic fast lock control signal generator responsive to the generated clock signal and a completed controlled change in power supply voltage indication signal, and operative to selectively apply the stabilizing control signal to the input of the variable clock signal generator.

10. The integrated circuit of claim 9, wherein the selectively driven charge pump comprises:

open feedback loop switch logic responsive to the phase adjust signal and the controlled change in power supply voltage indication signal, and operative to selectively open the feedback loop; and

a charge pump responsive to the open feedback loop switch logic and operative to provide the charge control signal to the variable clock signal generator.

11. The integrated circuit of claim 10, wherein the charge pump is further responsive to a reset indication signal, and operative to open the feedback loop.

13. The integrated circuit of claim 9, wherein the process corner control signal generator comprises a logic switch responsive to the chip reset indication signal and operative to selectively connect and disconnect the output of the process corner control generator to a power supply voltage.

14. The integrated circuit of claim 9, wherein the dynamic fast lock control signal generator is further responsive to a desired power supply voltage and wherein the dynamic supply voltage-based fast lock control signal generator comprises:

a frequency counter responsive to the generated clock signal and operative to determine the frequency of the generated clock signal;

process corner and stabilizing logic responsive to the frequency of the generated clock signal and operative to determine the process corner of the integrated circuit;

wherein the process corner and stabilizing logic is further responsive to the desired power supply voltage and the process corner of the integrated circuit, and operative to produce a control signal; and

a resistance divider network responsive to the control signal and operative to produce the stabilizing control signal.

15. The integrated circuit of claim 14, wherein the dynamic fast lock control signal generator further comprises:

a frequency threshold memory operably coupled to the process corner and stabilizing logic;

a look-up table operably coupled to the process corner and stabilizing logic;

wherein the process corner and stabilizing logic is responsive to the frequency of the generated clock signal and operative to access the frequency threshold memory to determine the process corner of the integrated circuit based on a comparison between the frequency of the generated clock signal and at least one threshold frequency accessed in the frequency threshold memory; and

wherein the process corner and stabilizing logic is responsive to the process corner and operative to access the look-up table to produce the control signal based upon the process corner and the desired power supply voltage.

16. An integrated circuit comprising:

a process corner control generator responsive to a chip reset indication signal and operative to produce a process corner control signal;

a system phase lock loop comprising a variable clock signal generator responsive to the process corner control signal and operative to produce a generated clock signal; and

process corner logic responsive to the generated clock signal and operative to determine the process corner of the integrated circuit.

17. The integrated circuit of claim 16 further comprising:

a frequency counter responsive to the generated clock signal and operative to determine the frequency of the generated clock signal; and

wherein the process corner logic is responsive to the frequency of the generated clock signal and operative to access a frequency threshold memory to determine the process corner of the integrated circuit based on a comparison between the frequency of the generated clock signal and at least one threshold frequency accessed in the frequency threshold memory.

18. A method for generating a clock signal using a clock generating circuit located on an integrated circuit having a feedback loop and a variable clock signal generator, the method comprising:

selectively opening the feedback loop in response to a controlled change in power supply voltage condition; and

selectively applying a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop.

19. The method of claim 18, wherein the method further comprises:

before selectively opening the feedback loop, determining the process corner of the integrated circuit; and

wherein selectively applying a stabilizing control signal comprises generating the stabilizing control signal based on the process corner of the integrated circuit.

20. A method for generating a clock signal using a clock generating circuit located on an integrated circuit having a feedback loop and a variable clock signal generator, the method comprising:

selectively opening the feedback loop in response to a controlled change in power supply voltage condition;

selectively applying a stabilizing control signal to the variable clock signal generator in response to opening the feedback loop;

selectively removing the stabilizing control signal from the variable clock signal generator in response to an absence of the controlled change in power supply voltage condition; and

selectively closing the feedback loop in response to the absence of the controlled change in power supply voltage condition.

21. The method of claim 20, wherein the controlled change in power supply voltage condition is detected by receipt of a controlled change in power supply voltage indication signal.

22. The method of claim 20, wherein selectively applying the stabilizing control signal to the variable clock signal generator in response to opening the feedback loop comprises selectively applying the stabilizing control signal to the variable clock signal generator in response to opening the feedback loop and in response to an absence of the controlled change in power supply voltage condition.

23. A method for generating a clock signal using a clock generating circuit located on an integrated circuit having a feedback loop and a variable clock signal generator, the method comprising:

using a system phase lock loop (PLL) of the clock generating circuit to determine a process corner of the integrated circuit;

receiving a desired power supply voltage;

selectively opening a feedback loop in response to a controlled change in power supply voltage indication signal;

in response to selectively opening the feedback loop, selectively applying a stabilizing control signal to the variable clock signal generator based on the determined process corner of the integrated circuit and the desired power supply voltage;

selectively removing the stabilizing control signal from the variable clock signal generator in response to a completed controlled change in power supply voltage indication signal; and

selectively closing the feedback loop in response to the controlled change in power supply voltage indication signal.

24. The method of claim 23, wherein using the system PLL to determine the process corner of the integrated circuit comprises:

selectively opening the feedback loop in response to a reset indication signal;

in response to opening the feedback loop, selectively applying a process corner control signal to the variable clock signal generator;

producing a generated clock signal having a frequency based on the process corner control signal;

comparing the generated clock signal frequency to at least one of a plurality of threshold frequencies; and

determining the process corner of the integrated circuit based on the comparison of the generated clock signal frequency and the at least one of the plurality of threshold frequencies.

25. The method of claim 24, wherein selectively applying a process corner control signal to the variable clock signal generator comprises applying a power supply voltage to the variable clock signal generator in response to a chip reset indication signal.

26. The method of claim 23, wherein selectively applying the stabilizing control signal to the variable clock signal generator comprises:

determining a control signal based on the process corner of the integrated circuit and a desired power supply voltage;

providing the control signal to a resistance divider network; and

producing the stabilizing control signal based on the control signal.

27. A method for determining a process corner of an integrated circuit comprising:

selectively opening a feedback loop of a system phase lock loop (PLL) in response to a reset condition;

selectively applying a process corner control signal to a variable clock signal generator of the system PLL in response to a chip reset condition;

producing a variable clock signal generator output having a frequency based upon the process corner control signal;

comparing the variable clock signal generator output frequency to at least one of a plurality of threshold frequencies; and

determining the process corner based on the comparison between the variable clock signal generator output frequency and at least one of the plurality of threshold frequencies.

28. The method of claim 27, wherein selectively opening a feedback loop of the system PLL in response to the reset condition further comprises receiving a reset indication signal a charge pump of the system PLL.

29. The method of claim 27, wherein selectively applying a process corner control signal to a variable clock signal generator of the system PLL in response to a chip reset condition further comprises receiving a chip reset indication signal.