Phase-locked loop

• US 20070120586A1
• Filed: 11/24/2006
• Published: 05/31/2007
• Est. Priority Date: 11/24/2005
• Status: Abandoned Application

• Current Assignee: Atmel Automotive GmbH (Microchip Technology Incorporated)
• Original Assignee: Atmel Automotive GmbH (Microchip Technology Incorporated)
• Inventors: Tyulpanov, Alexander
• Application Number:
  US11/603,992
• Publication Number:
  US 20070120586A1
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range

Abstract

A phase-locked loop with reduced settling time, in particular in or for a transceiver circuit of a tire pressure monitoring system, is disclosed, The phase-locked loop includes, sequentially arranged in a signal path, phase comparators for generating a phase difference signal by comparing a reference input signal and an output signal, loop filters for filtering the phase difference signal, and an oscillator controlled by the filtered phase difference signal for generating the output signal. The phase-locked loop has an adapting circuit for reducing the settling time at switch-on of the phase-locked loop, which adapting circuit correlates the actual switch-on of the phase-locked loop with the signal behavior of the reference input signal. A transceiver circuit of a tire pressure monitoring system is also disclosed.

Claims

1. A phase-locked loop having a reduced settling time for a transceiver circuit of a tire pressure monitoring system, the phase-locked loop comprising:

a phase comparator for generating a phase difference signal by comparing a reference input signal with an output signal;

a loop filter for filtering the phase difference signal;

an oscillator controlled by the filtered phase difference signal for generating the output signal; and

an adapting circuit for reducing the settling time at switch-on of the phase-locked loop, the adapting circuit correlating the actual switch-on of the phase-locked loop with the signal behavior of the reference input signal,

wherein the phase comparator, the loop filter, the oscillator and the adapting circuit are sequentially arranged in a signal path.

2. The phase-locked loop according to claim 1, wherein the adapting circuit provides at its output a first control signal by which, when the phase-locked loop is switched on, the oscillator is not switched in at least until there is a signal transition of the reference input signal.

3. The phase-locked loop according to claim 1, wherein the adapting circuit has a first input for coupling in the reference input signal and a second input for coupling in a switch-on signal, which puts the phase-locked loop into a state in which it can be switched on by a first control signal, and wherein the adapting circuit combines the reference input signal with the switch-on signal and generates therefrom the first control signal that switches on the phase-locked loop.

4. The phase-locked loop according to claim 3, wherein the adapting circuit has a latch or a flip-flop for providing the first control signal.

5. The phase-locked loop according to claim 1, wherein a feedback path with a divider located therein is provided, through which a feedback signal derived from the output signal by dividing down with a division factor (1/N) can be fed back into an input of the phase comparator.

6. The phase-locked loop according to claim 1, wherein the oscillator and/or the phase comparator and/or the divider has a control input for coupling in the first control signal through which the oscillator and/or the phase comparator and/or the divider, when the phase-locked loop is switched on, is switched in only at such time as a signal transition of the reference input signal occurs.

7. The phase-locked loop according to claim 1, wherein the oscillator is a voltage-controlled oscillator.

8. The phase-locked loop according to claim 1, wherein the loop filter is a low-pass filter.

9. The phase-locked loop according to claim 1, wherein the loop filter has a small bandwidth in a range up to 125 kHz.

10. The phase-locked loop according to claim 1, wherein the phase comparator is a phase detector or a phase/frequency detector.

11. The phase-locked loop according to claim 1, wherein at least one charge pump is arranged between the phase comparator and the loop filter.

12. The phase-locked loop according to claim 11, wherein a charge pump control circuit is provided, which, as specified by a second control signal that indicates whether the phase-locked loop is closed, produces a third control signal for driving the at least one charge pump.

13. The phase-locked loop according to claim 11, wherein at least two charge pumps are provided, wherein the first charge pump produces a smaller charge pump current than the second charge pump.

14. The phase-locked loop according to claim 13, wherein a maximum of one of the two charge pumps is activated, and the first charge pump is activated through a third control signal if the phase-locked loop is locked in, and/or the second charge pump is activated through the third control signal if the phase-locked loop is not locked in.

15. The phase-locked loop according to claim 1, wherein at least two phase comparators are provided, and wherein the first phase comparator is a phase detector and the second phase comparator is a phase/frequency detector.

16. The phase-locked loop according to claim 13, wherein the first charge pump follows the output of the phase detector and the second charge pump follows the output of the phase/frequency detector.

17. The phase-locked loop according to claim 1, wherein a closed loop detection circuit is provided, which detects whether the phase-locked loop is closed.

18. The phase-locked loop according to claim 5, wherein the divider divides the frequency and/or phase of the output signal by four.

19. The phase-locked loop according to claim 1, wherein a lock detection circuit is provided that detects whether the phase-locked loop is locked in, and which, in the case of a locked-in phase-locked loop, generates a lock control signal, and in the case of a phase-locked loop that is not locked in, generates a lock control signal that is inverted.

20. A transceiver circuit of a tire pressure monitoring system, the circuit comprising:

a device for generating and/or synchronizing a clock signal; and

a phase-locked loop in order to set up short-term data communication with another transceiver circuit of the same tire pressure monitoring system during operation thereof,

wherein the phase-locked loop comprises;

a phase comparator for generating a phase difference signal by comparing a reference input signal with an output signal;

a loop-filter for filtering the phase difference signal;

an oscillator controlled by the filtered phase difference signal for generating the output signal; and

an adapting circuit for reducing the settling time at switch-on of the phase-locked loop, the adapting circuit correlating the actual switch-on of the phase-locked loop with the signal behavior of the reference input signal,

wherein the phase comparator, the loop filter, the oscillator and the adapting circuit are sequentially arranged in a signal path.

21. The transceiver circuit according to claim 20, wherein the transceiver circuit is a transponder and is applied to a rim of a motor vehicle wheel.

22. The transceiver circuit according to claim 21, wherein the transponder is vulcanized into a rubber material of a tire of the wheel.