Replica bias circuit

• US 20070120600A1
• Filed: 06/13/2006
• Published: 05/31/2007
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Byun, Sang, Yu, Hyun
• Granted Patent: US 7,429,874 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• CPC Class Codes: H03F 2200/456 A scaled replica of a transistor being present in an amplifier
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

Claims

1. A replica bias circuit for applying a reference voltage to gates of target transistors constituting an electronic circuit, the replica bias circuit comprising:

a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and

a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit.

2. The replica bias circuit according to claim 1, wherein each constituent device on the replica path has a correspondence relationship with each constituent device on the current flow path.

3. The replica bias circuit according to claim 1, wherein the constituent device on the replica path and the constituent device on the current flow path are manufactured through the same manufacturing process.

4. The replica bias circuit according to claim 1, wherein the sub threshold voltage generator comprises:

a low voltage transistor; and

a sub threshold current forcer for allowing smaller current relative to a channel dimension of the low voltage transistor to flow into the low voltage transistor.

5. The replica bias circuit according to claim 4, wherein the sub threshold current forcer is connected in series with the low voltage transistor, and is a small current transistor having a channel dimension smaller than that of the low voltage transistor.

6. The replica bias circuit according to claim 1, wherein the replica path comprises at least one transistor for providing a current flow channel, and

the sub threshold voltage generator forces at least one of the transistors forming the replica path to operate in a saturation area.

7. The replica bias circuit according to claim 1, wherein the electronic circuit is a CMOS logic latch circuit having a multi-layer stacked current mode structure.

8. The replica bias circuit according to claim 1, wherein the electronic circuit is a CMOS logic circuit having a multi-layer stacked current mode structure.