Nonvolatile semiconductor memory device and its writing method

• US 20070121392A1
• Filed: 11/30/2006
• Published: 05/31/2007
• Est. Priority Date: 11/30/2005
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nawaki, Masaru
• Application Number:
  US11/607,633
• Publication Number:
  US 20070121392A1
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

There is provided a nonvolatile semiconductor memory device and its writing method capable of controlling an increase in threshold voltage due to effects of adjacent memory cells and performing stable readout operations even if miniaturization of semiconductor memory devices proceeds further. The device comprises a memory cell array 411 having memory cells in a row and column directions, a row selection circuit 412, a column selection circuit 411, and a control circuit 405 for exercising writing control on a selected memory cell by an external command input. The control circuit performs a threshold voltage control for writing a memory cell selected as a writing target to a first predetermined threshold voltage when receiving a first external write command, and performs another threshold voltage control for writing the selected memory cell to a second predetermined threshold voltage different from the first threshold voltage when receiving a second external write command.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array consisting of memory cells having a nonvolatile transistor capable of electrically writing, erasing and reading out information arranged in a matrix in a row direction and in a column direction;

a row selection circuit for selecting the memory cell in the row direction;

a column selection circuit for selecting the memory cell in the column direction; and

a control circuit for exercising a writing control on the memory cell selected by the row selection circuit and the column selection circuit by a command inputted from outside, wherein

the control circuit is configured to be able to receive a first external write command and a second external write command, and performs a first threshold voltage control for writing the memory cell selected as a writing target to a first predetermined threshold voltage when receiving the first external write command, and a second threshold voltage control for writing the memory cell selected as a writing target to a second predetermined threshold voltage that is different from the first threshold voltage when receiving the second external write command.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

the second threshold voltage is set within a predetermined range from a value derived from adding a variation of a threshold voltage to the first threshold voltage, and the variation of a threshold voltage is of the memory cell already written by the first threshold voltage control and caused by writing an adjacent memory cell.

3. The nonvolatile semiconductor memory device according to claim 1, wherein

the control circuit conducts the first threshold voltage control by applying a writing pulse based on a current comparison between the memory cell to be written and a first reference memory cell, and

the second threshold voltage control by applying a writing pulse based on a current comparison between the memory cell to be written and a second reference memory cell.

4. The nonvolatile semiconductor memory device according to claim 1, wherein

the control circuit conducts the first and second threshold voltage controls by using a same reference memory cell and applying different gate voltages between the first and second threshold voltage controls to a control gate of the memory cell or the reference memory cell.

5. A method of writing to the nonvolatile semiconductor memory device according to claim 1, the method comprising:

writing by the first external write command to a plurality of the memory cells selected as a writing target in the memory cell array; and

writing by the second external write command to the plurality of memory cells in the memory cell array written by the first external write command.

6. The method according to claim 5, wherein

an address and data of the memory cell to be written by the second external write command are the same as an address and data of the memory cell written by the first external write command.