Self-refresh period measurement circuit of semiconductor device

• US 20070121407A1
• Filed: 08/01/2006
• Published: 05/31/2007
• Est. Priority Date: 11/29/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Kyong
• Granted Patent: US 7,486,583 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations

Abstract

A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a shift register configured to receive an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, and delay the received oscillation signal by a unit self-refresh period to output a delayed oscillation signal, a period measurement start signal generator configured to receive the self-refresh signal and the oscillation signal and generate a period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period, and a refresh period output unit configured to receive the period measurement start signal and the delayed oscillation signal from the shift register and generate a refresh period output signal that is enabled for a period from a time that the period measurement start signal is enabled to a time that the delayed oscillation signal is enabled for the first time.

Claims

1. A self-refresh period measurement circuit of a semiconductor device comprising:

a delay device configured to receive an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, and delay the received oscillation signal by a unit self-refresh period to output a delayed oscillation signal;

a period measurement start signal generator configured to receive the self-refresh signal and the oscillation signal, and generate a period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period; and

a refresh period output unit configured to receive the period measurement start signal and the delayed oscillation signal from the delay device, and generate a refresh period output signal that is enabled for a period from a time that the period measurement start signal is enabled to a time that the delayed oscillation signal is enabled for the first time.

2. The self-refresh period measurement circuit as set forth in claim 1, wherein the delay device is a shift register, and the shift register shifts the oscillation signal by the unit self-refresh period.

3. The self-refresh period measurement circuit as set forth in claim 2, wherein the shift register is enabled by a test mode signal for the self-refresh period measurement.

4. The self-refresh period measurement circuit as set forth in claim 1, wherein the period measurement start signal generator comprises:

a pull-up device configured to pull a specific node up in response to the self-refresh signal;

a pull-down device configured to pull the node down in response to the oscillation signal;

a latch configured to latch a signal of the node; and

a signal generator configured to output a pulse signal that is enabled for a predetermined period from a time that an output signal from the latch makes a level transition, as the period measurement start signal, in response to the level transition of the output signal from the latch.

5. The self-refresh period measurement circuit as set forth in claim 4, wherein the signal generator comprises:

a delay configured to delay the output signal from the latch by the predetermined period;

a buffer configured to buffer the output signal from the latch; and

a logic device configured to buffer a logic operation with respect to an output signal from the delay and an output signal from the buffer.

6. The self-refresh period measurement circuit as set forth in claim 5, wherein the buffer is an inverter, and the inverter performs an inverting operation.

7. The self-refresh period measurement circuit as set forth in claim 5, wherein the logic device performs a NOR operation.

8. The self-refresh period measurement circuit as set forth in claim 1, wherein the refresh period output unit comprises:

a first logic device configured to perform a logic operation with respect to the period measurement start signal and a test mode signal for the self-refresh period measurement;

a second logic device configured to perform a logic operation with respect to the delayed oscillation signal and the test mode signal; and

a latch including third and fourth logic devices interconnected in latch form, the third logic device receiving an output signal from the first logic device at its one input terminal, the fourth logic device receiving an output signal from the second logic device at its one input terminal.

9. The self-refresh period measurement circuit as set forth in claim 8, wherein each of the first to fourth logic devices is a NAND gate.

10. The self-refresh period measurement circuit as set forth in claim 8, wherein the refresh period output unit operates in response to an enabled state of the test mode signal.

11. The self-refresh period measurement circuit as set forth in claim 10, wherein the refresh period output unit further comprises voltage level hold means for holding an output terminal of the latch at a predetermined voltage level in response to the test mode signal.

12. A self-refresh period measurement circuit of a semiconductor device comprising:

a delay device configured to receive an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, delay the received oscillation signal by a predetermined integer multiple of a unit self-refresh period to output a first delayed oscillation signal, and delay the received oscillation signal by the predetermined integer multiple of the unit self-refresh period plus the unit self-refresh period to output a second delayed oscillation signal;

a period measurement start signal generator configured to receive the self-refresh signal and the first delayed oscillation signal, and generate a period measurement start signal for setting a time that the first delayed oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period; and

a refresh period output unit configured to receive the period measurement start signal and the second delayed oscillation signal, and generate a refresh period output signal that is enabled for a period from a time that the period measurement start signal is enabled to a time that the second delayed oscillation signal is enabled for the first time.

13. The self-refresh period measurement circuit as set forth in claim 12, wherein the delay device is a shift register block, the shift register block including a plurality of shift registers.

14. The self-refresh period measurement circuit as set forth in claim 13, wherein the shift registers are connected in series, each of the shift registers shifting an input signal by the unit self-refresh period.

15. The self-refresh period measurement circuit as set forth in claim 13, wherein the shift register block is enabled by a test mode signal for the self-refresh period measurement.

16. The self-refresh period measurement circuit as set forth in claim 12, wherein the period measurement start signal generator comprises:

a pull-up device configured to pull a specific node up in response to the self-refresh signal;

a pull-down device configured to pull the node down in response to the first delayed oscillation signal;

a latch configured to latch a signal of the node; and

a signal generator configured to output a pulse signal that is enabled for a predetermined period from a time that an output signal from the latch makes a level transition, as the period measurement start signal, in response to the level transition of the output signal from the latch.

17. The self-refresh period measurement circuit as set forth in claim 16, wherein the signal generator comprises:

a delay configured to delay the output signal from the latch by the predetermined period;

a buffer configured to buffer the output signal from the latch; and

a logic device configured to perform a logic operation with respect to an output signal from the delay and an output signal from the buffer.

18. The self-refresh period measurement circuit as set forth in claim 17, wherein the buffer is an inverter, and the inverter performs an inverting operation.

19. The self-refresh period measurement circuit as set forth in claim 17, wherein the logic device performs a NOR operation.

20. The self-refresh period measurement circuit as set forth in claim 12, wherein the refresh period output unit comprises:

a first logic device configured to perform a logic operation with respect to the period measurement start signal and a test mode signal for the self-refresh period measurement;

a second logic device configured to perform a logic operation with respect to the second delayed oscillation signal and the test mode signal; and

a latch including third and fourth logic devices interconnected in latch form, the third logic device receiving an output signal from the first logic device at its one input terminal, the fourth logic device receiving an output signal from the second logic device at its one input terminal.

21. The self-refresh period measurement circuit as set forth in claim 20, wherein each of the first to fourth logic devices is a NAND gate.

22. The self-refresh period measurement circuit as set forth in claim 20, wherein the refresh period output unit further comprises voltage level hold means for holding an output terminal of the latch at a predetermined voltage level in response to the test mode signal.

23. A self-refresh period measurement circuit of a semiconductor device comprising:

delay means for receiving an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, delaying the received oscillation signal by a unit self-refresh period to output a first delayed oscillation signal, by a predetermined integer multiple of the unit self-refresh period to output a second delayed oscillation signal, and delaying the received oscillation signal by the predetermined integer multiple of the unit self-refresh period plus the unit self-refresh period to output a third delayed oscillation signal;

a first period measurement start signal generator for receiving the self-refresh signal and the oscillation signal and generating a first period measurement start signal for setting a time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period;

a second period measurement start signal generator for receiving the self-refresh signal and the second delayed oscillation signal, and generating a second period measurement start signal for setting a time that the second delayed oscillation signal is enabled for the first time as the start time for the self-refresh period measurement;

a first refresh period output unit for receiving the first period measurement start signal and the first delayed oscillation signal, and generating a first refresh period output signal that is enabled for a period from a time that the first period measurement start signal is enabled to a time that the first delayed oscillation signal is enabled for the first time; and

a second refresh period output unit for receiving the second period measurement start signal and the third delayed oscillation signal, and generating a second refresh period output signal that is enabled for a period from a time that the second period measurement start signal is enabled to a time that the third delayed oscillation signal is enabled for the first time.

24. The self-refresh period measurement circuit as set forth in claim 23, further comprising a signal combiner for combining the first refresh period output signal and the second refresh period output signal to output a final refresh period output signal.

25. The self-refresh period measurement circuit as set forth in claim 24, wherein the signal combiner performs an OR operation.

26. The self-refresh period measurement circuit as set forth in claim 23, wherein the delay means comprises a plurality of shift registers connected in series, each of the shift registers shifting an input signal by the unit self-refresh period.

27. The self-refresh period measurement circuit as set forth in claim 23, wherein the delay means is operated in response to a result of a logic operation of a plurality of test mode signals for the self-refresh period measurement.

28. The self-refresh period measurement circuit as set forth in claim 23, wherein:

the first period measurement start signal generator comprises;

a first pull-up device for pulling a first node up in response to the self-refresh signal;

a first pull-down device for pulling the first node down in response to the oscillation signal;

a first latch for latching a signal of the first node; and

a first signal generator for outputting a first pulse signal that is enabled for a predetermined period from a time that an output signal from the first latch makes a level transition, as the first period measurement start signal, in response to the level transition of the output signal from the first latch; and

the second period measurement start signal generator comprises;

a second pull-up device for pulling a second node up in response to the self-refresh signal;

a second pull-down device for pulling the second node down in response to the second delayed oscillation signal;

a second latch for latching a signal of the second node; and

a second signal generator for outputting a second pulse signal that is enabled for the predetermined period from a time that an output signal from the second latch makes a level transition, as the second period measurement start signal, in response to the level transition of the output signal from the second latch.

29. The self-refresh period measurement circuit as set forth in claim 28, wherein at least one of the first signal generator and second signal generator comprises:

a delay for delaying the output signal from the first latch or second latch by the predetermined period;

a buffer for buffering the output signal from the first latch or second latch; and

a logic device for performing a logic operation with respect to an output signal from the delay and an output signal from the buffer.

30. The self-refresh period measurement circuit as set forth in claim 29, wherein the buffer is an inverter which performs an inverting operation, and the logic device performs a NOR operation.

31. The self-refresh period measurement circuit as set forth in claim 23, wherein the first refresh period output unit comprises:

a first logic device for performing a logic operation with respect to the first period measurement start signal and a first test mode signal for the self-refresh period measurement;

a second logic device for performing a logic operation with respect to the first delayed oscillation signal and the first test mode signal; and

a first latch including third and fourth logic devices interconnected in latch form, the third logic device receiving an output signal from the first logic device at its one input terminal, the fourth logic device receiving an output signal from the second logic device at its one input terminal; and

wherein the second refresh period output unit comprises;

a fifth logic device for performing a logic operation with respect to the second period measurement start signal and a second test mode signal for the self-refresh period measurement;

a sixth logic device for performing a logic operation with respect to the third delayed oscillation signal and the second test mode signal; and

a second latch including seventh and eighth logic devices interconnected in latch form, the seventh logic device receiving an output signal from the fifth logic device at its one input terminal, the eighth logic device receiving an output signal from the sixth logic device at its one input terminal.

32. The self-refresh period measurement circuit as set forth in claim 31, wherein each of the first to eighth logic devices is a NAND gate.

33. The self-refresh period measurement circuit as set forth in claim 31, wherein:

the first refresh period output unit further comprises first voltage level hold means for holding an output terminal of the first latch at a predetermined voltage level in response to the first test mode signal; and

the second refresh period output unit further comprises second voltage level hold means for holding an output terminal of the second latch at the predetermined voltage level in response to the second test mode signal.

34. A self-refresh period measurement circuit of a semiconductor device comprising:

a period measurement start signal generator for configured to receive a self-refresh signal and an oscillation signal that is periodically enabled by a first width after the self-refresh signal is enabled, to allow a self-refresh operation to be performed, and generate a period measurement start signal that is enabled by a second width at a time that the oscillation signal is enabled for the first time, to set the time that the oscillation signal is enabled for the first time as a start time for measurement of a self-refresh period; and

a refresh period output unit configured to receive the period measurement start signal and the oscillation signal, and generate a refresh period output signal that is enabled for a period from the time that the period measurement start signal is enabled to a time that the oscillation signal is enabled for the second time.

35. The self-refresh period measurement circuit as set forth in claim 34, wherein the second width is larger than the first width.

36. The self-refresh period measurement circuit as set forth in claim 35, wherein the period measurement start signal generator comprises:

a pull-up device configured to pull a specific node up in response to the self-refresh signal;

a pull-down device configured to pull the node down in response to the oscillation signal;

a latch configured to latch a signal of the node; and

a signal generator configured to output a pulse signal that is enabled by the second width from a time that an output signal from the latch makes a level transition, as the period measurement start signal, in response to the level transition of the output signal from the latch.

37. The self-refresh period measurement circuit as set forth in claim 36, wherein the signal generator comprises:

a delay configured to delay the output signal from the latch by the second width;

a buffer configured to buffer the output signal from the latch; and

a logic device configured to perform a logic operation with respect to an output signal from the delay and an output signal from the buffer.

38. The self-refresh period measurement circuit as set forth in claim 37, wherein the buffer is an inverter, and the inverter performs an inverting operation.

39. The self-refresh period measurement circuit as set forth in claim 37, wherein the logic device performs a NOR operation.

40. The self-refresh period measurement circuit as set forth in claim 34, wherein the refresh period output unit comprises:

a first logic device configured to perform a logic operation with respect to the period measurement start signal and a test mode signal for the self-refresh period measurement;

a second logic device configured to perform a logic operation with respect to the oscillation signal and the test mode signal; and

a latch including third and fourth logic devices interconnected in latch form, the third logic device receiving an output signal from the first logic device at its one input terminal, the fourth logic device receiving an output signal from the second logic device at its one input terminal.

41. The self-refresh period measurement circuit as set forth in claim 40, wherein each of the first to fourth logic devices is a NAND gate.

42. The self-refresh period measurement circuit as set forth in claim 40, wherein the refresh period output unit further comprises voltage level hold means for holding an output terminal of the latch at a predetermined voltage level in response to the test mode signal.