Phase-locked loop for stably adjusting frequency-band of voltage-controlled oscillator and phase locking method

• US 20070121774A1
• Filed: 11/13/2006
• Published: 05/31/2007
• Est. Priority Date: 11/25/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hoon, Lee, Jung, Suh, Chung
• Granted Patent: US 7,471,159 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A phase-locked loop (PLL) for stably adjusting a frequency band of a voltage-controlled oscillator and a phase locking method. In the PLL, a frequency band controller alters the frequency band selection digital value in response to an input clock signal and an oscillation control signal generated from an LPF of a basic PLL circuit, and thus a voltage-controlled oscillator of the basic PLL circuit alters the frequency of an output clock signal in response to the oscillation control signal and the frequency band selection digital value. The output clock signal is rapidly and stably phase-locked at a target frequency depending on the frequency band selection digital value.

Claims

1. A phase-locked loop comprising:

a basic phase-locked loop circuit comprising a voltage-controlled oscillator (VCO), the basic phase-locked loop circuit generating an output clock signal which is phase-locked with an input clock signal using the VCO which oscillates in response to an oscillation control signal and changes an oscillation frequency band depending on a frequency band selection digital value; and

a frequency band controller which generates the frequency band selection digital value in response to the input clock signal and the oscillation control signal.

2. The phase-locked loop of claim 1, wherein the frequency band controller comprises:

a comparator which compares the oscillation control signal with a first reference voltage to generate an up-count signal, and compares the oscillation control signal with a second reference voltage to generate a down-count signal;

a stabilization controller which generates an enable signal to update an operating frequency region of the VCO in response to the input clock signal and the oscillation control signal; and

a counter which receives the up-count signal and the down-count signal from the comparator, selectively outputs the up-count signal in response to the enable signal so as to increment the frequency band selection digital value, and selectively outputs the down-count signal in response to the enable signal so as to decrement the frequency band selection digital value.

3. The phase-locked loop of claim 2, wherein the stabilization controller calculates an interval where the oscillation control signal is higher than the first reference voltage or lower than the second reference voltage, and determines the operating frequency region of the VCO to be updated according to a calculation result to thereby generate the enable signal to select one of the down-count signal and the up-count signal.

4. The phase-locked loop of claim 3, wherein the stabilization controller counts the input clock signal to generate at least one critical time period, and compares the generated at least one critical time period with the calculated interval to determine the operating frequency region of the VCO.

5. The phase-locked loop of claim 4, wherein the stabilization controller generates the enable signal which is activated at a certain time point if the oscillation control signal goes beyond a corresponding frequency region based on the determined operating frequency region of the VCO.

6. The phase-locked loop of claim 2, wherein the stabilization controller comprises:

a critical time generator which counts the input clock signal to generate at least one critical time period;

a frequency band excess time calculator which calculates an interval where the oscillation control signal is higher than the first reference voltage or lower than the second reference voltage;

a frequency band update decision section which determines the operating frequency region of the VCO to be updated according to the generated at least one critical time period and the calculated interval; and

a decision section which generates the enable signal which is activated at a certain time point if the oscillation control signal goes beyond a corresponding frequency region based on the determined operating frequency region of the VCO.

7. The phase-locked loop of claim 1, wherein the frequency band controller comprises:

a comparator which compares the oscillation control signal and a first reference voltage to generate an up-count signal, and compares the oscillation control signal and a second reference voltage to generate a down-count signal;

a stabilization controller which selectively outputs a part of the up-count signal and selectively outputs a part of the down-count signal depending on at least one critical time period generated on a basis of the input clock signal; and

a counter which increments the frequency band selection digital value in response to the output up-count signal and decrements the frequency band selection digital value in response to the output down-count signal.

8. The phase-locked loop of claim 7, wherein the stabilization controller comprises:

a critical time generator which counts the input clock signal to generate at least one critical time period;

a frequency band update decision section which generates a signal which is activated after the generated at least one critical time period from a time point when if the up-count signal or the down-count signal is activated; and

a decision section which selectively outputs the up-count signal or selectively outputs the down-count signal depending on the signal generated by the frequency band update decision section.

9. The phase-locked loop of claim 8, wherein the frequency band update decision section comprises:

a first decision section which generates a first signal which is activated after the generated at least one critical time period from a time point when the up-count signal is activated; and

a second decision section which generates a second signal which is activated after the generated at least one critical time period from a time point when the down-count signal is activated.

10. The phase-locked loop of claim 1, wherein each of the basic PLL circuit and the frequency band controller is a digital circuit.

11. A method of phase-locking an input clock signal using a voltage-controlled oscillator (VCO) which is operated in response to an oscillation control signal and a frequency band selection digital value, the method comprising:

receiving the input clock signal;

processing, using the VCO, the input clock signal and an output clock signal which is fed back from the VCO to generate the oscillation control signal;

deciding the frequency band selection digital value in response to the input clock signal and the oscillation control signal; and

changing an oscillation frequency band of the VCO depending on the decided frequency band selection digital value to thereby generate the output clock signal having a frequency which is phase-locked at a certain target frequency.

12. The method of claim 11, wherein the deciding the frequency band selection digital value comprises:

comparing the oscillation control signal and a first reference voltage to generate an up-count signal, and comparing the oscillation control signal and a second reference voltage to generate a down-count signal;

generating an enable signal to update an operating frequency region of the VCO in response to the input clock signal and the oscillation control signal; and

selectively outputting the up-count signal in response to the enable signal so as to increment the frequency band selection digital value in response to the output up-count signal; and

selectively outputting the down-count signal in response to the enable signal so as to decrement the frequency band selection digital value in response to the output down-count signal.

13. The method of claim 12, wherein the generating the enable signal comprises:

calculating an interval where the oscillation control signal is higher than the first reference voltage or lower than the second reference voltage, and determining the operating frequency region of the VCO to be updated according to a calculation result; and

generating the enable signal to select either the down-count signal or the up-count signal depending on the determined operating frequency region.

14. The method of claim 13 further comprising:

counting the input clock signal to generate at least one critical time period; and

comparing the generated at least one critical time period with the calculated interval to determine the operating frequency region of the VCO.

15. The method of claim 14 further comprising generating the enable signal which is activated at a certain time point of when the oscillation control signal goes beyond a corresponding frequency region based on the decided operating frequency region of the VCO.

16. The method of claim 11, wherein the deciding the frequency band selection digital value comprises:

comparing the oscillation control signal and a first reference voltage to generate an up-count signal, and comparing the oscillation control signal and a second reference voltage to generate a down-count signal;

selectively outputting a part of the up-count signal and selectively outputting a part of the down-count signal depending on at least one critical time period generated on a basis of the input clock signal;

incrementing the frequency band selection digital value in response to the output up-count signal; and

decrementing the frequency band selection digital value in response to the output down-count signal.

17. The method of claim 16, wherein the selectively outputting the part of the up-count signal and selectively outputting the part of the down-count signal depending on the at least one critical time period generated on the basis of the input clock signal comprises:

counting the input clock signal to generate at least one critical time period;

generating a signal which is activated after the generated at least one critical time period, from a time point when the up-count signal or the down-count signal is activated;

selectively outputting the up-count signal depending on the activated signal; and

selectively outputting the down-count signal depending on the activated signal.

18. A computer readable recording medium storing a program for implementing a method of phase-locking an input clock signal using a voltage-controlled oscillator (VCO) which is operated in response to an oscillation control signal and a frequency band selection digital value, the method comprising:

receiving the input clock signal;

processing, using the VCO, the input clock signal and an output clock signal which is fed back from the VCO to generate the oscillation control signal;

deciding the frequency band selection digital value in response to the input clock signal and the oscillation control signal; and

changing an oscillation frequency band of the VCO depending on the decided frequency band selection digital value to thereby generate the output clock signal having a frequency which is phase-locked at a certain target frequency.