METHODS OF FORMING SEMICONDUCTOR DEVICES USING EMBEDDED L-SHAPE SPACERS

• US 20070122988A1
• Filed: 11/29/2005
• Published: 05/31/2007
• Est. Priority Date: 11/29/2005
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Inventors: Luo, Zhijiong, Ajmera, Atul, Teh, Young
• Granted Patent: US 7,759,206 B2
• Time in Patent Office: Days
• US Class Current: 438/303
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.

Claims

1. A method of forming a semiconductor device, comprising:

defining an L-shaped spacer on each side of a gate region of a substrate; and

embedding said L-shaped spacers in an oxide layer so that said oxide layer extends over a portion of said substrate a predetermined distance from a lateral edge of said L-shaped spacer.

2. The method of claim 1, wherein said predetermined distance is up to about 600 Angstroms.

3. The method of claim 1, wherein said predetermined distance is between about 200 to about 400 Angstroms.

4. The method of claim 1, further comprising:

etching said oxide layer to reveal a top portion of said gate region and a top portion of said L-shaped spacer; and

implanting ions in said substrate to define an implant region at opposite sides of said oxide layer.

5. The method of claim 4, further comprising annealing said implant regions to define source-drain regions, said source-drain regions each having an edge that is less than about 200 Angstroms away from said lateral edge.

6. The method of claim 5, wherein said edge is co-planar with said lateral edge.

7. The method of claim 5, further comprising:

removing said oxide layer; and

forming a silicide region having an inner edge substantially co-planar to said lateral edge.

8. The method of claim 7, further comprising depositing a nitride stress layer over said silicide regions, said L-shaped spacer, and said top portion of said gate region.

9. A method of forming a semiconductor device, comprising:

depositing a first oxide layer over a gate region and a semiconductor substrate;

depositing a nitride layer on said first oxide layer;

depositing a second oxide layer on said nitride layer;

etching said first oxide layer, said second oxide layer, and said nitride layer to form an L-shaped spacer on each side of said gate region; and

depositing a third oxide layer on said L-shaped spacers so that said third oxide layer covers a portion of said semiconductor substrate a predetermined distance from a lateral edge of said L-shaped spacer.

10. The method of claim 9, wherein said predetermined distance is up to about 600 Angstroms.

11. The method of claim 9, wherein said predetermined distance is between about 200 to about 400 Angstroms.

12. The method of claim 9, further comprising:

etching said third oxide layer to reveal a top portion of said gate region and a top portion of said L-shaped spacer; and

implanting ions in said substrate to define an implant region in said substrate at said predetermined distance from said lateral edge.

13. The method of claim 12, further comprising annealing said implant region to define a source-drain region, said source-drain region having an edge that is less than about 200 Anstroms from said lateral edge.

14. The method of claim 13, wherein said edge is co-planar with said lateral edge.

15. The method of claim 13, further comprising:

removing said second and third oxide layers; and

forming a silicide region having an edge substantially co-planar to said lateral edge.

16. The method of claim 15, further comprising depositing a nitride stress layer over said silicide region, said L-shaped spacer, and said top portion of said gate region.

17. A semiconductor device comprising:

a gate region on a semiconductor substrate;

an L-shaped spacer defined on at least one side of said gate region, said L-shaped spacer having a lateral edge;

a source-drain region having an edge that is less than about ±

200 Anstroms from said lateral edge; and

a silicide region having an edge that is substantially co-planar to said lateral edge.

18. The semiconductor device of claim 17, wherein said silicide region is free of etch induced damage.

19. The semiconductor device of claim 17, further a nitride stress layer over said silicide region, said L-shaped spacer, and said gate region.