ELECTROLESS PLATING OF METAL CAPS FOR CHALCOGENIDE-BASED MEMORY DEVICES

• US 20070123039A1
• Filed: 01/29/2007
• Published: 05/31/2007
• Est. Priority Date: 11/03/2004
• Status: Active Grant

• Current Assignee: John Moore, Patricia Elkins, Rita Klein
• Original Assignee: John Moore, Patricia Elkins, Rita Klein
• Inventors: Moore, John, Klein, Rita, Elkins, Patricia
• Granted Patent: US 7,550,380 B2
• Time in Patent Office: Days
• US Class Current: 438/652
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe

Abstract

A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.

Claims

1. A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device comprising, forming a layer of a first conductive material over a substrate, depositing an insulating layer over said first conductive material and said substrate, forming an opening in said insulating layer to expose at least a portion of said first conductive material, depositing a second conductive material over said insulating layer and within said opening, removing portions of said second conductive material to form a conductive area within said opening, recessing said conductive area within said opening to a level below an upper surface of said insulating layer, forming a cap of a third conductive material over the recessed conductive area within said opening, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stack.

2. A method as claimed in claim 1 wherein said cap of third conductive material is formed by electroless plating.

3. A method as claimed in claim 2 including activating the surface of the recessed conductive area.

4. A method as claimed in claim 1 in which said second conductive material comprises tungsten.

5. A method as claimed in claim 1 including the step of depositing a refractory metal or refractory metal nitride layer in said opening prior to the deposition of said second conductive material.

6. A method as claimed in claim 5 in which said refractory metal comprises titanium.

7. A method as claimed in claim 5 in which said refractory metal nitride comprises titanium nitride.

8. A method as claimed in claim 1 including removing portions of said cap to planarize said cap.

9. A method as claimed in claim 1 in which said cap is formed to have a thickness of from about 200 to about 500 angstroms.

10. A method as claimed in claim 1 in which said insulating layer is selected from the group consisting of borophosphosilicate glass, tetraethylorthosilicate glass, and silicon nitride.

11. A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device comprising, providing an insulating layer over a substrate, said insulating layer having an opening therein, said opening exposing at least a portion of a first conductive material on said substrate, depositing a second conductive material over said insulating layer and within said opening, removing portions of said second conductive material to form a conductive area within said opening, recessing said conductive area within said opening to a level below an upper surface of said insulating layer, forming a cap of a third conductive material over the recessed conductive area within said opening, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stack.

12. A method of forming a conductive metal interconnect for a semiconductor circuit comprising, providing a semiconductor structure having semiconductor devices formed thereon, forming an insulating layer over said semiconductor structure, forming a trench in said insulating layer down to said semiconductor structure exposing at least a portion of said semiconductor devices, substantially filling said trench with tungsten, recessing said tungsten to a level below the upper surface of said insulating layer, electrolessly depositing a metal cap over the recessed tungsten, depositing a stack of a chalcogenide based memory cell material over said cap, and depositing a conductive material over said chalcogenide stack.

13. A method as claimed in claim 12 including activating the surface of the recessed tungsten prior to electrolessly depositing said metal cap.

14. A method as claimed in claim 12 including removing portions of said cap to planarize said cap.

15. A conductive interconnect for a chalcogenide-based memory device comprising, an insulating layer having an opening therein on a semiconductor substrate, a recessed tungsten layer in said opening, an electrolessly deposited metal cap on said tungsten layer, a stack of a chalcogenide based memory cell material over said cap, and a conductive material over said chalcogenide stack.

16. A conductive interconnect as claimed in claim 15 in which said metal cap is planarized to be coplanar with an upper surface of said insulating layer.

17. A processor-based system comprising a processor, and a chalcogenide-based memory device coupled to said processor, said chalcogenide-based memory device comprising an insulating layer having an opening therein on a semiconductor substrate, a recessed tungsten layer in said opening, an electrolessly deposited metal cap on said tungsten layer, a stack of a chalcogenide based memory cell material over said cap, and a conductive material over said chalcogenide stack.

18. A system as claimed in claim 17 in which said metal cap is planarized to be coplanar with an upper surface of said insulating layer.