Semiconductor device and operating method thereof

• US 20070123189A1
• Filed: 11/07/2006
• Published: 05/31/2007
• Est. Priority Date: 11/25/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko, Kato, Kiyoshi
• Granted Patent: US 7,912,439 B2
• Time in Patent Office: Days
• US Class Current: 455/333
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H10K 10/50 Bistable switching devices

Abstract

In an organic memory which is included in a radio chip formed from a thin film, data are written to the organic memory by a signal inputted with a wired connection, and the data is read with a signal by radio transmission. A bit line and a word line which form the organic memory are each selected by a signal which specifies an address generated based on the signal inputted with a wired connection. A voltage is applied to a selected memory element. Thus writing is performed. Reading is performed by a clock signal or the like which are generated from a radio signal.

Claims

1. A semiconductor device comprising:

a radio signal input portion comprising a power supply circuit and a clock generator, the radio signal input portion generates a first clock signal, a first power potential and a second power potential;

a logic circuit portion electrically connected to the radio signal input portion, the logic circuit portion generates a reading signal and a second clock signal;

a memory region electrically connected to the radio signal input portion and the logic circuit portion, the memory region having an organic memory, a reading signal input portion, a writing signal input portion, a clock signal input portion, a first power potential input portion, a second power potential input portion and a writing power potential input portion; and

an external signal input portion for electrically connecting the memory region to an external circuit.

5. The semiconductor device according to claim 1, further comprising a diode electrically connected between the first power potential input portion and the writing power potential input portion.

6. The semiconductor device according to claim 1, further comprising a first resistor element electrically connected between the first power potential input portion and the writing signal input portion.

7. The semiconductor device according to claim 1, further comprising a second resistor element electrically connected between the logic circuit portion and the clock signal input portion.

11. The semiconductor device according to claim 1, further comprising a third resistor element electrically connected between the logic circuit portion and the reading signal input portion.

15. The semiconductor device according to claim 1, further comprising a first switch electrically connected between the logic circuit portion and the clock signal input portion.

19. The semiconductor device according to claim 1, further comprising a second switch electrically connected between the logic circuit portion and the reading signal input portion.

23. The semiconductor device according to claim 1, further comprising a protection circuit electrically connected between the memory region and the external signal input portion.

27. The semiconductor device according to claim 1,

wherein the organic memory comprises a plurality of memory cells, and each of the memory cells comprises an organic compound layer and a switching element electrically connected to the organic compound layer.

31. The semiconductor device according to claim 1, wherein the radio signal input portion comprises a demodulation circuit and a modulation circuit.

2. A semiconductor device comprising:

a radio signal input portion;

a logic circuit portion electrically connected to the radio signal input portion;

a memory region electrically connected to the radio signal input portion and the logic circuit portion, the memory region having an organic memory, a reading signal input portion, a writing signal input portion, a clock signal input portion, a first power potential input portion, a second power potential input portion and a writing power potential input portion; and

an external signal input portion for electrically connecting the memory region to an external circuit,

wherein, in a reading mode, the radio signal input portion receives a radio signal and supplies a first power potential to the first power potential input portion and a second power potential to the second power potential input portion, and the logic circuit portion outputs a clock signal to the clock signal input portion and a reading signal to the reading signal input portion, and

wherein, in a writing mode, the first power potential, the second power potential, a writing power potential, a writing signal and the clock signal are supplied to the memory region through the external signal input portion.

8. The semiconductor device according to claim 2, further comprising a second resistor element electrically connected between the logic circuit portion and the clock signal input portion.

12. The semiconductor device according to claim 2, further comprising a third resistor element electrically connected between the logic circuit portion and the reading signal input portion.

16. The semiconductor device according to claim 2, further comprising a first switch electrically connected between the logic circuit portion and the clock signal input portion.

20. The semiconductor device according to claim 2, further comprising a second switch electrically connected between the logic circuit portion and the reading signal input portion.

24. The semiconductor device according to claim 2, further comprising a protection circuit electrically connected between the memory region and the external signal input portion.

28. The semiconductor device according to claim 2,

wherein the organic memory comprises a plurality of memory cells, and each of the memory cells comprises an organic compound layer and a switching element electrically connected to the organic compound layer.

32. The semiconductor device according to claim 2, wherein the radio signal input portion comprises a demodulation circuit and a modulation circuit.

3. A semiconductor device comprising:

a radio signal input portion;

a logic circuit portion electrically connected to the radio signal input portion;

a memory region electrically connected to the radio signal input portion and the logic circuit portion, the memory region having an organic memory, a reading signal input portion, a writing signal input portion, a clock signal input portion, a first power potential input portion, a second power potential input portion and a writing power potential input portion;

an external signal input portion for electrically connecting the memory region to an external circuit; and

a diode electrically connected between the first power potential input portion and the writing power potential input portion,

wherein, in a reading mode, the radio signal input portion receives a radio signal and supplies a first power potential to the first power potential input portion, a second power potential to the second power potential input portion, and the first power potential to the writing power potential input portion through the diode, and the logic circuit portion outputs a clock signal to the clock signal input portion and a reading signal to the reading signal input portion, and

wherein, in a writing mode, the first power potential, the second power potential, a writing power potential, a writing signal and the clock signal are supplied to the memory region through the external signal input portion.

9. The semiconductor device according to claim 3, further comprising a second resistor element electrically connected between the logic circuit portion and the clock signal input portion.

13. The semiconductor device according to claim 3, further comprising a third resistor element electrically connected between the logic circuit portion and the reading signal input portion.

17. The semiconductor device according to claim 3, further comprising a first switch electrically connected between the logic circuit portion and the clock signal input portion.

21. The semiconductor device according to claim 3, further comprising a second switch electrically connected between the logic circuit portion and the reading signal input portion.

25. The semiconductor device according to claim 3, further comprising a protection circuit electrically connected between the memory region and the external signal input portion.

29. The semiconductor device according to claim 3,

wherein the organic memory comprises a plurality of memory cells, and each of the memory cells comprises an organic compound layer and a switching element electrically connected to the organic compound layer.

33. The semiconductor device according to claim 3, wherein the radio signal input portion comprises a demodulation circuit and a modulation circuit.

4. A semiconductor device comprising:

a radio signal input portion;

a logic circuit portion electrically connected to the radio signal input portion;

a memory region electrically connected to the radio signal input portion and the logic circuit portion, the memory region having an organic memory, a reading signal input portion, a writing signal input portion, a clock signal input portion, a first power potential input portion, a second power potential input portion and a writing power potential input portion;

an external signal input portion for electrically connecting the memory region to an external circuit; and

a first resistor element electrically connected between the first power potential input portion and the writing signal input portion,

wherein, in a reading mode, the radio signal input portion receives a radio signal and supplies a first power potential to the first power potential input portion, a second power potential to the second power potential input portion, and the first power potential to the writing signal input portion through the first resistor element, and the logic circuit portion outputs a clock signal to the clock signal input portion and a reading signal to the reading signal input portion, and

wherein, in a writing mode, the first power potential, the second power potential, a writing power potential, a writing signal and the clock signal are supplied to the memory region through the external signal input portion.

10. The semiconductor device according to claim 4, further comprising a second resistor element electrically connected between the logic circuit portion and the clock signal input portion.

14. The semiconductor device according to claim 4, further comprising a third resistor element electrically connected between the logic circuit portion and the reading signal input portion.

18. The semiconductor device according to claim 4, further comprising a first switch electrically connected between the logic circuit portion and the clock signal input portion.

22. The semiconductor device according to claim 4, further comprising a second switch electrically connected between the logic circuit portion and the reading signal input portion.

26. The semiconductor device according to claim 4, further comprising a protection circuit electrically connected between the memory region and the external signal input portion.

30. The semiconductor device according to claim 4,

wherein the organic memory comprises a plurality of memory cells, and each of the memory cells comprises an organic compound layer and a switching element electrically connected to the organic compound layer.

34. The semiconductor device according to claim 4, wherein the radio signal input portion comprises a demodulation circuit and a modulation circuit.

35. An operating method of a semiconductor device, the semiconductor device comprising:

a radio signal input portion;

a logic circuit portion electrically connected to the radio signal input portion;

a memory region electrically connected to the radio signal input portion and the logic circuit portion, the memory region having an organic memory; and

an external signal input portion for electrically connecting the memory region to an external circuit, the operating method comprising;

writing data to the memory region by a first power potential, a second power potential, a writing power potential, a writing signal and a clock signal input through the external signal input portion by wired connection; and

reading the data from the memory region by the first power potential and the second power potential from the radio signal input portion, and the clock signal and reading signal from the logic circuit portion.

36. An operating method of a semiconductor device, the semiconductor device comprising:

a radio signal input portion;

a logic circuit portion electrically connected to the radio signal input portion;

a memory region electrically connected to the radio signal input portion and the logic circuit portion, the memory region having an organic memory, a first power potential input portion and a writing power potential input portion;

an external signal input portion for electrically connecting the memory region to an external circuit; and

a diode electrically connected between the first power potential input portion and the writing power potential input portion, the operating method comprising;

writing data to the memory region by a first power potential, a second power potential, a writing power potential, a writing signal and a clock signal input through the external signal input portion by wired connection; and

reading the data from the memory region by the first power potential and the second power potential from the radio signal input portion, and the clock signal and reading signal from the logic circuit portion while inputting the first power potential to the writing power potential input portion through the diode.

37. An operating method of a semiconductor device, the semiconductor device comprising:

a radio signal input portion;

a logic circuit portion electrically connected to the radio signal input portion;

a memory region electrically connected to the radio signal input portion and the logic circuit portion, the memory region having an organic memory, a writing signal input portion and a first power potential input portion;

an external signal input portion for electrically connecting the memory region to an external circuit; and

a resistor element electrically connected between the first power potential input portion and the writing signal input portion, the operating method comprising;

writing data to the memory region by a first power potential, a second power potential, a writing power potential, a writing signal and a clock signal input through the external signal input portion by wired connection; and

reading the data from the memory region by the first power potential and the second power potential from the radio signal input portion, and the clock signal and reading signal from the logic circuit portion while inputting the first power potential to the writing signal input portion through the resistor element.