Automatic yielding on lock contention for multi-threaded processors

• US 20070124545A1
• Filed: 11/29/2005
• Published: 05/31/2007
• Est. Priority Date: 11/29/2005
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Herrenschmidt, Benjamin, Russell, Paul, Blanchard, Anton
• Application Number:
  US11/288,862
• Publication Number:
  US 20070124545A1
• Time in Patent Office: Days
• US Class Current: 711/152
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A method and system are provided for managing processor resources in a multi-threaded processor. When attempting to acquire a lock on a shared resource, an initial test is conducted to determine if there is a lock address for the shared resource in a lock table. If it is determined that the address is in the lock table, the lock is in use by another thread. Processor resources associated with the lock requesting thread are mitigated so that processor resources may focus on the lock holding thread prior to the requesting thread spinning on the lock. Processor resources are assigned to the threads based upon the assigned priorities, thereby allowing the processor to allocate more resources to a thread assigned a high priority and fewer resources to a thread assigned a low priority.

Claims

1. A method for mitigating overhead on a multi-threaded processor, comprising:

determining presence of a lock address in a lock table for a shared resource;

adjusting allocation of processor resources to a thread holding said lock responsive to presence of said lock address in said lock table.

2. The method of claim 1, further comprising placing said lock address in said lock table responsive to absence of said lock address in said lock table.

3. The method of claim 1, further comprising removing said address from said lock table to release said lock.

4. The method of claim 1, further comprising issuing a sync instruction to remove said lock address from memory.

5. The method of claim 1, wherein said lock table is stored in volatile memory.

6. The method of claim 1, wherein the step of adjusting allocation of processor resources to a thread holding said lock includes increasing a priority level of said thread holding said lock, and lowering a priority level of a non-lock holding thread.

7. A computer system comprising:

a multi-threaded processor;

a lock table adapted to store a lock address for a shared resource held by a thread; and

a manager adapted to communicate with said processor to adjust allocation of processor resources from a lock requesting thread to a thread in possession of said lock in response to presence of said lock address in said lock table.

8. The system of claim 7, further comprising said lock address adapted to be placed in said lock table in response to absence of a lock address in said lock table from another thread.

9. The system of claim 7, further comprising a release instruction adapted to remove said lock address from said lock table.

10. The system of claim 7, further comprising a sync instruction adapted to remove all lock addresses from memory.

11. The system of claim 7, wherein said lock table is stored in volatile memory.

12. The system of claim 7, wherein adjustment of processor resources is adapted to allocate more resources to said thread in possession of said lock.

13. The system of claim 7, wherein adjustment of processor resources is adapted to allocate fewer resources to a thread spinning on said lock.

14. An article comprising:

a computer readable medium;

instructions in said medium for a thread to request a lock on a shared resource from a multi-threaded processor;

instructions in said medium for evaluating a lock table to determine presence of a lock address responsive to said instruction requesting said lock; and

instructions in said medium for a processor managing said resource to adjust allocation of processor resources to a lock holding thread responsive to presence of said lock address in said lock table.

15. The article of claim 14, further comprising instructions in said medium for placing a lock address in said lock table responsive to absence of said lock address in said lock table.

16. The article of claim 14, further comprising a release instruction in said medium for removing said lock address from said lock table.

17. The article of claim 14, further comprising a sync instruction in said medium for removing all lock addresses from memory.

18. The article of claim 14, wherein said lock table is stored in volatile memory.

19. The article of claim 14, wherein said instruction to adjust allocation of processor resources to a lock holding thread includes increasing processor resources for said lock holding thread.

20. The article of claim 14, wherein said instruction to adjust allocation of processor resources to lock holding thread includes decreasing processor resources for a non-lock holding thread.