Bit field selection instruction

• US 20070124631A1
• Filed: 04/06/2006
• Published: 05/31/2007
• Est. Priority Date: 11/08/2005
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Boggs, Darrell, Thornton, Gregory, Fogg, Chad, Anderson, Tyler
• Application Number:
  US11/400,434
• Publication Number:
  US 20070124631A1
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

A digital signal processor having a generalized bit field extraction instruction which can be used to perform a bit field selection operation, a rotate left operation, a rotate right operation, a shift left operation, a logical shift right operation, an arithmetic shift right operation, and so forth.

Claims

1. A method whereby a processor executes an instruction, the method comprising:

(a) extracting an N-bit contiguous bit field from,

high order bits of a first source operand designated by a first source operand designator of the instruction, and

low order bits of a second source operand designated by a second source operand designator of the instruction; and

(b) writing the N-bit contiguous bit field to a destination designated by a destination designator of the instruction;

wherein the first and second source operands are treated as a 2N-bit operand.

2. The method of claim 1 wherein:

the first source operand comprises a register exactly N bits wide;

the second source operand comprises a register exactly N bits wide; and

the destination comprises a register exactly N bits wide.

3. The method of claim 1 wherein:

the N-bit contiguous bit field is extracted from a position specified by a third source operand designated by a third source operand designator of the instruction.

4. The method of claim 3 wherein:

the third source operand specifies an offset as a number of bits from an end of the 2N-bit operand.

5. The method of claim 4 wherein:

the third source operand specifies the offset as a number of bits from a least significant bit end of the first source operand.

6. The method of claim 4 wherein:

the first source operand comprises a 128-bit register;

the second source operand comprises a 128-bit register; and

the destination comprises a 128-bit register.

7. The method of claim 1 wherein:

the first and second source operand designators designate a same source operand;

whereby the instruction accomplishes a rotate operation upon the source operand.

8. The method of claim 1 wherein:

the first and second source operand designators designate different source operands.

9. The method of claim 8 wherein:

the N-bit contiguous bit field is extracted from a position specified by a third source operand designated by a third source operand designator of the instruction;

the third source operand specifies a position of a least significant bit of the N-bit contiguous bit field.

10. The method of claim 8 wherein:

the first source operand designator designates a first source operand containing all zeroes;

whereby the instruction accomplishes a shift left operation upon the second source operand.

11. The method of claim 10 wherein:

the first source operand comprises a dedicated ZeroReg register which always contains zeroes during operation of the processor.

12. The method of claim 10 wherein:

the N-bit contiguous bit field is extracted from a position specified by a third source operand designated by a third source operand designator of the instruction;

wherein the first and second source operands each comprise respective N-bit registers;

wherein the third source operand contains a value N−

X; and

wherein X comprises a shift count of the shift left operation.

13. The method of claim 8 wherein:

the second source operand designator designates a second source operand containing all zeroes;

whereby the instruction accomplishes a shift right operation upon the first source operand.

14. The method of claim 13 wherein:

the second source operand comprises a dedicated ZeroReg register which always contains zeroes during operation of the processor.

15. The method of claim 8 wherein:

all bits of the second source operand contain a same binary value as a most significant bit of the first source operand;

whereby the instruction accomplishes an arithmetic shift right of the first source operand.

16. The method of claim 15 wherein:

the second source operand comprises a dedicates All1Reg register which always contains ones during operation of the processor.

17. The method of claim 8 wherein:

the first source operand comprises a first fixed content register which always contains a first fixed content during operation of the processor; and

the second source operand comprises a second fixed content register which always contains a second fixed content during operation of the processor.

18. The method of claim 1 wherein:

the first and second source operands each comprises a respective N-bit register;

a third source operand of the instruction identifies an offset X; and

the method further comprises

if the instruction is for performing a leftward operation, using one of X and N−

X as an offset from an end of the 2N-bit operand from which the bit field is selected; and

if the instruction is for performing a rightward operation, using the other of X and N−

X as an offset from an end of the 2N-bit operand from which the bit field is selected.

19. The method of claim 18 wherein:

the third source operand is designated by a third source operand designator of the instruction and contains the offset X as an offset from a least significant bit end of the 2N-bit register;

if the instruction is for performing a leftward operation, subtracting X from N to generate an offset Y from a most significant bit end of the first source operand.

20. The method of claim 19 further comprising:

subtracting X from N to generate a X−

N result regardless of whether the instruction is for performing a leftward operation or a rightward operation; and

selecting between the X−

N result and X, depending upon whether the instruction is for performing a leftward operation or a rightward operation, respectively.

21. The method of claim 19 further comprising:

during a single execution of the instruction, performing a plurality of the extracting and the writing in SIMD manner.

22. A method whereby a processor having a plurality of N-bit registers executes an instruction, the method comprising:

decoding an opcode of the instruction;

in response to decoding the opcode, determining that the instruction is a bit field selection instruction;

copying Z highest-order bits from a first N-bit source register designated by a first source operand designator of the instruction into Z low-order bits of an N-bit destination register designated by a destination designator of the instruction;

copying Y lowest-order bits from a second N-bit source register designated by a second source operand designator of the instruction into Y high-order bits of the N-bit destination register;

wherein Y+Z=N; and

wherein the instruction specifies which Y+Z bit field to copy into the destination register.

23. The method of claim 22 wherein:

the instruction specifies the Y+Z bit field as an offset X from an end of one of the first and second source registers.

24. The method of claim 23 wherein:

X specifies an offset from a low order bit end of the first source register.

25. The method of claim 23 wherein:

the instruction expressly specifies X.

26. The method of claim 23 wherein:

the instruction expressly specifies X in a third N-bit source operand register designated by a third source operand designator in the instruction.

27. The method of claim 26 wherein:

for rightward operations, the third N-bit source operand register holds X; and

for leftward operations, the third N-bit source operand register holds N−

X.

28. The method of claim 23 wherein:

by the first and second source operand identifiers designating a same N-bit register, the instruction performs a rotate operation.

29. The method of claim 23 wherein:

by one of the first and second source operand identifiers designating a register holding data, and the other of the first and second source operand identifiers designating a register holding N bits of a same value, the instruction performs a shift operation.

30. The method of claim 29 wherein:

by the first source operand identifier designating a register holding all zeroes and the second source operand identifier designating the register holding the data, the instruction performs a shift left operation.

31. The method of claim 29 wherein:

by the second source operand identifier designating a register holding all zeroes and the first source operand identifier designating the register holding the data, the instruction performs a logical shift right operation.

32. The method of claim 29 wherein:

by the second source operand identifier designating a register holding N bits having a same value as a highest order bit of the register holding the data, and the first source operand identifier designating the register holding the data, the instruction performs an arithmetic shift right operation.

33. The method of claim 22 wherein:

copying Z bits and copying Y bits each comprises a SIMD operation.