Memory devices including dielectric thin film and method of manufacturing the same

• US 20070126045A1
• Filed: 12/01/2006
• Published: 06/07/2007
• Est. Priority Date: 12/05/2005
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Ryu, Min Ki, Kim, Ansoon, Ah, Chil Seong, Yu, Han Young, Choi, Sung-Yool
• Granted Patent: US 7,960,774 B2
• Time in Patent Office: Days
• US Class Current: 257/310
• CPC Class Codes: H01G 7/06 having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors electrets H01G7/02
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/31637 Deposition of Tantalum oxides, e.g. Ta2O5
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator

Abstract

A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.

Claims

1. A memory device comprising:

a bottom electrode;

at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and

an top electrode disposed on the dielectric thin film.

2. The memory device of claim 1, wherein different space-charge limit currents flow in the dielectric thin film according to the charge trap densities.

3. The memory device of claim 2, wherein the space-charge limit current is controlled by an impurity added to the dielectric layer.

4. The memory device of claim 1, wherein the dielectric layer is composed of:

a dielectric formed of TiO_2, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, PdO, or a material in which at least one of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Hf, Nb, Ta, Pd, and La group elements is added to TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, or PdO, as an impurity;

a dielectric of ABO₃ type;

or

a dielectric consisting of a material having a perovskite structure, except the ABO₃ type, and impurities added to the material.

5. The memory device of claim 1, wherein the charge trap density ranges from 10¹⁷/cm³ to 10²¹/cm³.

6. The memory device of claim 1, wherein the dielectric thin film has a thickness of 3 nm to 100 nm.

7. The memory device of claim 1, wherein a dielectric constant of the dielectric layer ranges from 3 to 1000.

8. A method of manufacturing a memory device, comprising the steps of:

forming a bottom electrode;

forming at least one dielectric thin film having a plurality of dielectric layers with different charge trap densities from each other on the bottom electrode; and

forming an top electrode on the dielectric thin film.

9. The method of claim 8, wherein the step of forming the dielectric thin film comprises the steps of:

forming a lower dielectric layer on the bottom electrode; and

forming an upper dielectric layer using a dielectric equal to or different from the lower dielectric layer on the lower dielectric layer.

10. The method of claim 8, wherein the step of forming the dielectric thin film comprises the step of forming an intermediate dielectric layer using a dielectric equal to at least one of the lower and upper dielectric layers or a dielectric different from the lower and upper dielectric layers, between the lower dielectric layer formed on the bottom electrode and the upper dielectric layer formed on the lower dielectric layer.

11. The method of claim 10, wherein the intermediate dielectric layer acts as a barrier which prevents traps included in the lower and upper dielectric layers from moving.

12. The method of claim 9, wherein when the lower dielectric layer, the intermediate dielectric layer, and the upper dielectric layer are formed of the same dielectric, deposition conditions of the respective dielectric layers are different from each other.

13. The method of claim 12, wherein the deposition condition is at least one of a deposition temperature, a deposition time, a deposition rate and a deposition method.

14. The method of claim 8, wherein the dielectric thin film has a thickness of 3 nm to 100 nm.

15. The method of claim 8, wherein the dielectric layer is formed of a dielectric having a dielectric constant ranging from 3 to 1000.

16. The method of claim 8, wherein the dielectric layer is composed of:

a dielectric formed of TiO_2, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, PdO, or a material in which at least one of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Hf, Nb, Ta, Pd, and La group elements is added to TiO₂, ZrO₂, HfO₂, V₂O₅, Nb₂O₅, Ta₂O₅, NiO, or PdO, as an impurity;

a dielectric of ABO₃ type;

or

a dielectric consisting of a material having a perovskite structure, except the ABO₃ type, and impurities added to the material.