Semiconductor device and method of forming the same

• US 20070126048A1
• Filed: 11/16/2006
• Published: 06/07/2007
• Est. Priority Date: 11/17/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Hun, Kang, Sung-Taeg, Han, Jeong-Uk, Jeon, Hee-Seog
• Granted Patent: US 7,800,158 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Claims

1. A semiconductor device comprising:

a non-volatile memory device formed on a substrate;

a first selection device formed on the substrate at one side of the non-volatile memory device; and

a floating junction formed in the substrate between the non-volatile memory device and the first selection device;

wherein a gate of the first selection device is formed of a single-layered conductive layer.

2. The semiconductor device of claim 1, wherein the non-volatile memory device comprises a stacked gate structure having a floating gate, a control gate, and an insulation layer formed between the floating gate and the control gate.

3. The semiconductor device of claim 2, wherein the floating gate of the non-volatile memory device and the gate of the first selection device are formed of the same material.

4. The semiconductor device of claim 2, further comprising a drain formed in the substrate outside the non-volatile memory device opposite to the floating junction, and a source formed in the substrate outside the first selection device opposite to the floating junction.

5. The semiconductor device of claim 2, wherein the insulation layer of the non-volatile memory device comprises a silicon oxide layer, a silicon nitride layer, or a silicon oxide layer.

6. The semiconductor device of claim 2, further comprising a spacer formed on one sidewall of the stacked gate structure in the non-volatile memory device adjacent to the gate of the first selection device, covering the floating junction and extending toward a sidewall of the gate in the first selection device.

7. The semiconductor device of claim 6, further comprising a second spacer formed on the other sidewall in the gate of the first selection device opposite to the spacer, the spacer formed on the one sidewall of the non-volatile memory device having a height higher than that of the second spacer formed on the other sidewall.

8. The semiconductor device of claim 2, wherein a drain of the non-volatile memory device is connected to a bit line and a source of the selection device is electrically connected to a common source line.

9. The semiconductor device of claim 6, wherein the gate of the first selection device and the floating gate of the stacked gate structure of the non-volatile memory device are formed of the same material and have a substantially identical height.

10. The semiconductor device of claim 6, further comprising an oxide layer between the spacer and the stacked gate structure of the non-volatile memory device.

11. The semiconductor device of claim 2, further comprising:

a second selection device formed on the substrate at the other side of the non-volatile memory device, and including a gate formed of a single-layered conductive layer; and

a second floating junction formed on the substrate between the gate of the second selection device and the non-volatile memory device.

12. The semiconductor device of claim 11, further comprising a first spacer formed on sidewalls of the stacked gate structure in the non-volatile memory device, covering the first and second floating junction;

and

a second spacer formed on a sidewall of the first and second selection devices having a height lower than that of the first spacer.

13. A method of forming a semiconductor device, comprising:

forming a first conductive layer pattern on a substrate;

forming a stacked pattern including an inter-gate insulation layer pattern and a second conductive layer pattern on the first conductive layer pattern;

forming a mask insulation layer pattern on the first conductive layer pattern spaced apart from the stacked pattern;

removing the first conductive layer pattern outside the stacked pattern and the mask insulation layer pattern to form a floating gate below the stacked pattern, and to form a selection gate below the mask insulation layer pattern; and

forming a floating junction on the substrate between the floating gate and the selection gate.

14. The method of claim 13, wherein the forming of the mask insulation layer comprises:

forming a spacer on at least one sidewall of the stacked pattern;

forming the mask insulation layer pattern on the first conductive layer pattern exposed outside the spacer; and

removing the spacer.

15. The method of claim 14, wherein the forming of the spacer on at least one sidewall of the stacked pattern comprises:

forming an insulation layer for the spacer;

forming a photoresist pattern exposing a sidewall of the stacked pattern with the spacer thereon; and

etching the insulation layer for a spacer exposed by the photoresist pattern.

16. The method of claim 14, wherein the forming of the spacer on at least one sidewall of the stacked pattern comprises:

forming an insulation layer for the spacer; and

etching the insulation layer for the spacer,

wherein the spacer is formed on both sidewalls of the stacked pattern, the selection gate is formed on the substrate in both sides of the floating gate, the floating junction is formed between the floating gate and the selection gates on both sides of the floating gate.

17. The method of claim 14, wherein the forming of the spacer on at least one sidewall of the stacked pattern comprises:

forming an insulation layer for the spacer;

etching the insulation layer for a spacer to form spacers on both sidewalls of the stacked pattern;

forming a mask pattern covering one of the spacers and exposing another spacer;

removing the spacer exposed by the mask pattern; and

removing the mask pattern.

18. The method of claim 15, further comprising forming an oxide layer on the both sidewalls of the stacked pattern before the forming of the insulation for the spacer.

19. The method of claim 15, wherein the insulation layer for the spacer is formed of a silicon nitride layer.

20. The method of claim 19, further comprising forming an oxide layer on the both sidewall of the stacked pattern before the forming the insulation layer for the spacer.

21. The method of claim 14, wherein the mask insulation layer pattern is formed using a thermal oxidation process on the first conductive layer pattern exposed outside the spacer.

22. The method of claim 13, further comprising:

forming a spacer on the stacked pattern and the selection gate sidewall after the forming of the impurity junction; and

forming a drain on a sidewall of the stacked pattern not adjacent to the floating junction, and a source on a sidewall of the selection gate not adjacent to the floating junction through an ion implantation process,

wherein the spacer in a stacked gate sidewall adjacent to the floating junction covers the floating junction, and is extended toward the selection gate sidewall.

23. A method of forming a semiconductor device, comprising:

forming a conductive layer pattern on a substrate;

forming a stacked pattern including an inter-layer insulation layer and a control gate on the conductive layer pattern;

forming a spacer on at least one sidewall of the stacked pattern;

forming a mask insulation layer pattern on the conductive layer pattern exposed outside of the spacer;

removing the spacer;

etching the conductive layer pattern outside the stacked pattern to form a floating gate below the stacked pattern and to form a selection gate below the mask insulation layer pattern; and

performing an ion implantation process to form a floating junction on a substrate between the floating gate and the selection gate, and also to form a source and a drain on the substrate outside the floating gate and the selection gate not adjacent to the floating junction.

24. The method of claim 23, further comprising forming an oxide layer on both sidewalls of the stacked pattern before the forming of the spacer.

25. The method of claim 23, wherein the inter-layer insulation layer includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

26. The method of claim 23, wherein the forming of the mask insulation layer pattern comprises performing a thermal oxidation process on the conductive layer pattern exposed outside the spacer.

27. The method of claim 23, wherein the spacer is formed on both sidewalls of the stacked pattern;

the selection gate is formed on the substrate in both sides of the floating gate; and

the floating junction region is formed between the floating gate and the selection gates in the both sides of the floating gate.

28. A semiconductor device comprising:

a non-volatile memory device including a gate insulation layer, a floating gate, an inter-layer insulation layer, and a control gate on a substrate;

a selection device formed at one side of the non-volatile memory device;

a floating junction shared between the non-volatile memory device and the selection device;

a first sidewall spacer formed on a sidewall of the non-volatile memory device; and

a second sidewall spacer formed on a sidewall of the selection device, and having a height lower than that of the first sidewall spacer.

29. The semiconductor device of claim 28, wherein the selection device comprises a selection gate formed of a material identical to that of the floating gate of the memory device and having a height identical to that of the first sidewall spacer.

30. The semiconductor device of claim 28, wherein the non-volatile memory device and the selection device further comprise a source and a drain.

31. The semiconductor device of claim 29, wherein a drain of the non-volatile memory device is connected to the bit line and a source of the selection device is connected to a common source line.

32. The semiconductor device of claim 30, further comprising another selection device connected electrically to the common source line, and another non-volatile memory device with a drain connected electrically to the bit line.

33. The semiconductor device of claim 31, further comprising another selection device formed on the other side of the non-volatile memory device.