Trench insulated gate field effect transistor

• US 20070126055A1
• Filed: 11/26/2004
• Published: 06/07/2007
• Est. Priority Date: 11/29/2003
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hijzen, Erwin, Hueting, Raymond
• Application Number:
  US10/580,625
• Publication Number:
  US 20070126055A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The invention relates to a trench MOSFET with drain (8), drift (10) body (12) and source (14) regions. The drift region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the drift region (10) and a gate electrode (32) next to the body region (12).

Claims

1. An insulated gate field effect transistor, comprising:

a semiconductor body having opposed first and second major surfaces;

a source region of first conductivity type at the first major surface;

a body region of second conductivity type opposite to the first conductivity type under the source region;

a drift region of first conductivity type under the body region;

a drain region of first conductivity type under the drift region, so that the source, body, drift and drain regions regions extend in that order from the first major surface towards the second major surface; and

insulated trenches extending from the first major surface towards the second major surface past the source region and the body region into the drift region, each trench having sidewalls, and including insulator on the sidewalls, at least one conductive gate electrode adjacent to the body region separated from the body region by a gate insulator, and at least one conductive field plate electrode adjacent to the drift region separated from the drift region by a field plate insulator, and a gate-field plate insulator separating the field plate from the gate,

wherein the source regions and trenches define a pattern of cells across the first major surface; and

the doping concentration in the drift region increases from the part of the drift region adjacent to the body region to the part of the drift region adjacent to the drain region the doping concentration in the drift region being at least 50 times greater adjacent to the drain region than adjacent to the body region.

2. An insulated gate field effect transistor according to claim 1 in which the gate electrode is of conductive semiconductor doped to be the second conductivity type.

3. An insulated gate field effect transistor according to claim 1 wherein the gate electrode has side pieces spaced apart adjacent to the sidewalls on either side of the trench and a top piece spanning the gap between the side pieces.

4. An insulated gate field effect transistor according to claim 1 wherein the breakdown voltage is less than or equal to 30V.

5. An insulated gate field effect transistor according to claim 1 wherein the pattern of cells defined by the source regions and trenches arranged across the first major surface is a pattern in which cells repeat in more than one direction across the surface to form a three-dimensional cell structure.

6. An insulated gate field effect transistor according to claim 5 wherein the cells are arranged in a hexagonal pattern.

7. An insulated gate field effect transistor according to claim 1 further comprising a trench filled with conductive material extending through the source region to the body region to connect the source contact to the source region and the body region.

8. An insulated gate field effect transistor according to claim 7 further comprising

a doped contact region of second conductivity type in the body region in contact with the conductive material in the trench, the doping concentration in the doped contact region being higher than the doping in the rest of the body region.

9. An insulated gate field effect transistor according to claim 1 wherein the thickness of the insulator thickness adjacent to the field plate electrode is greater than the thickness of the insulator adjacent to the gate electrode.

10. An insulated gate field effect transistor according to claim 1 wherein the cell pitch is not greater than 1 micron.

11. An insulated gate field effect transistor according to claim 1 wherein the first conductivity type is n-type, the second conductivity type is p-type and the gate is of p-type doped polysilicon.

12. An insulated gate field effect transistor according to claim 1 wherein the field plate oxide thickness is in the range 0.6 to 1 micron and the gate oxide thickness is in the range 0.2 to 0.5 micron.

13. An insulated gate field effect transistor according to claim 1 wherein the field plate electrode is connected to the source.

14. An insulated gate field effect transistor according to claim 1 further comprising

a field plate terminal connected to the field plate for controlling the field plate voltage independently.