TRENCH STRUCTURE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING IT

• US 20070126056A1
• Filed: 08/31/2006
• Published: 06/07/2007
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz
• Granted Patent: US 7,723,782 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A trench structure semiconductor device is disclosed. In one embodiment, field electrode devices are arranged in a trench structure, in direct spatial proximity in comparison with essentially planar or smooth conditions, have an enlarged common interface region with an insulation material in between, whereby a comparatively stronger electrical coupling of the directly adjacent field electrode devices is achieved.

Claims

1. A trench structure semiconductor device, comprising:

a semiconductor material region with a surface region;

at least one trench structure with a wall region and a bottom region in the semiconductor material region;

a plurality of field electrode devices are formed in the interior of the trench structure as an electrode arrangement in a manner spaced apart and electrically insulated from one another and from the wall region of the trench structure by means of an insulation region;

spatially directly adjacent and mutually adjoining field electrode devices with an enlarged common interface region with an insulation material in between; and

a stronger capacitive electrical coupling or greater capacitance of directly adjacent and mutually adjoining field electrode devices is thereby formed in comparison with substantially planar and/or smooth conditions.

2. The trench structure semiconductor device as claimed in claim 1, in which the enlarged common interface region is formed by means of an increased roughness of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field electrode devices in the interface region.

3. The trench structure semiconductor device as claimed in claim 2, in which the increased roughness is formed in the region of at least one of the field electrode devices, so that the insulation region has a homogeneous thickness, in particular.

4. The trench structure semiconductor device as claimed claim 1, in which the enlarged common interface region is formed by means of one or a plurality of cutouts of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field plate electrode devices in the interface region.

5. The trench structure semiconductor device as claimed in claim 1, in which the enlarged common interface region is formed by means of one or a plurality of elevations of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field plate electrode devices in the interface region.

6. The trench structure semiconductor device as claimed in claim 4, in which cutouts and/or elevations are in each case formed in the material of a field electrode device, so that the insulation has a homogeneous thickness, in particular.

7. The trench structure semiconductor device as claimed in claim 4, in which cutouts and/or elevations of one of the mutually opposite interfaces in the material of a first field electrode device in the common interface region with a second, directly adjacent field electrode device adjoining the first are formed such that they cooperate or are in engagement in each case with corresponding elevations and/or cutouts of the directly adjacent and adjoining interface of the directly adjacent, adjoining and opposite interface in the material of the second field electrode device directly adjacent to and adjoining the first field electrode device in the common interface region, so that the insulation has a homogeneous thickness, in particular.

8. The trench structure semiconductor device as claimed in claim 4, in which—

viewed in cross section—

the mutually opposite interfaces of spatially directly adjacent and mutually adjoining field electrode devices are formed such that they cooperate or are intermeshed in comb-like fashion or in comb-shaped fashion.

9. The trench structure semiconductor device as claimed in claim 4, in which—

viewed in cross section—

the mutually opposite interfaces of spatially directly adjacent and mutually adjoining field electrode devices are formed such that they cooperate or are intermeshed in y-like fashion or in y-shaped fashion or in the form of a tuning fork.

10. The trench structure semiconductor device as claimed in claim 1, in which the trench structures are formed in a manner proceeding from the surface region of the semiconductor material region essentially in a first extension direction, which runs perpendicular to the surface region of the semiconductor material region, into the semiconductor material region.

11. The trench structure semiconductor device as claimed in claim 10, in which the field electrode devices of the electrode arrangement are formed as a stringing together of field electrode devices in the first extension direction in the interior of the trench structure.

12. The trench structure semiconductor device as claimed in claim 1, in which the trench structures are formed essentially in a second extension direction, which runs parallel to the surface region of the semiconductor material region, in the semiconductor material region.

13. The trench structure semiconductor device as claimed in claim 1, in which the field electrode device is formed in potential-free fashion or in floating fashion.

14. The trench structure semiconductor device as claimed in claim 1, in which a further electrode device, and in particular a control electrode device or a gate electrode device, is formed in the interior of the trench structure in a manner facing the surface region of the semiconductor material region and in a manner spatially separated and electrically insulated from the electrode arrangement of the plurality of field electrode devices by the insulation region and from the wall region of the trench structure, from the bottom region of the trench structure and/or from the semiconductor material region.

15. The trench structure semiconductor device as claimed in claim 14, in which the further electrode device is at a fixed electrical potential, in particular at source potential.

16. The trench structure semiconductor device as claimed in claim 1, which is formed as a device or as a combination of devices from the group consisting of a FET, a MOSFET, a trench transistor, a field plate transistor, a vertical transistor, a vertical trench transistor, an IGBT device, a p-channel transistor, a bipolar transistor, a diode device and a Schottky diode device.

17. The trench structure semiconductor device as claimed in claim 1, in which a pillar region doped oppositely to the doping of the surroundings is formed in the semiconductor material region and outside the trench structure and spatially at a distance from the latter, proceeding from the surface region of the semiconductor material region, the pillar region extending into the interior of the semiconductor material region.

18. The trench structure semiconductor device as claimed in claim 1, in which pairs of spatially directly adjacent field electrode devices which, in a common interface region, adjoin one another and are opposite one another are formed, relative to one another, in a targeted manner with differing degrees of pairwise electrical coupling or capacitance between the field electrode devices of the pairs of spatially directly adjacent field electrode devices which, in a common interface region, adjoin one another and are opposite one another, with respect to one another, in particular by means of a correspondingly targeted variation of the thickness of the insulation provided between the field electrode devices.

19. The trench structure semiconductor device as claimed in claim 1, in which the field electrode devices are formed such that they are electrically connected to one another via zener diodes or in high-impedance fashion in the trench structure or in an edge region.

20. A method for producing a trench structure semiconductor device, comprising:

forming a semiconductor material region with a surface region;

forming at least one trench structure with a wall region and a bottom region in the semiconductor material region;

forming, in the interior of the trench structure, a plurality of field electrode devices as an electrode arrangement in a manner spaced apart and electrically insulated from one another and from the wall region of the trench structure by means of an insulation region;

forming spatially directly adjacent and mutually adjoining field electrode devices with an enlarged common interface region with an insulation material in between; and

forming thereby a stronger capacitive electrical coupling or greater capacitance of directly adjacent and mutually adjoining field electrode devices in comparison with essentially planar and/or smooth conditions.

21. A method for producing a trench structure semiconductor device as claimed in claim 20, comprising:

forming the enlarged common interface region by means of an increased roughness of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field electrode devices in the interface region.

22. The method as claimed in claim 21, comprising:

forming the increased roughness in the region of at least one of the field electrode devices, so that the insulation region has a homogeneous thickness, in particular.

23. The method as claimed in claim 20, comprising:

forming the enlarged common interface region by means of one or a plurality of cutouts of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field plate electrode devices in the interface region.

24. The method as claimed in claim 20, comprising:

forming the enlarged common interface region by means of one or a plurality of elevations of at least one of the mutually opposite interfaces in the material of spatially directly adjacent and mutually adjoining field plate electrode devices in the interface region.

25. The method as claimed in claim 23, comprising:

forming cutouts and/or elevations in each case in the material of a field electrode device, so that the insulation has a homogeneous thickness, in particular.

26. The method as claimed in claim 20, comprising:

forming cutouts and/or elevations of one of the mutually opposite interfaces in the material of a first field electrode device in the common interface region with a second, directly adjacent field electrode device adjoining the first such that they cooperate or are in engagement in each case with corresponding elevations and/or cutouts of the directly adjacent and adjoining interface of the directly adjacent, adjoining and opposite interface in the material of the second field electrode device directly adjacent to and adjoining the first field electrode device in the common interface region, so that the insulation has a homogeneous thickness, in particular.

27. The method as claimed in claim 20, comprising:

forming the mutually opposite interfaces of spatially directly adjacent and mutually adjoining field electrode devices such that they cooperate or are intermeshed in comb-like fashion or in comb-shaped fashion.

28. The method as claimed in claim 20, comprising:

forming the mutually opposite interfaces of spatially directly adjacent and mutually adjoining field electrode devices such that they cooperate or are intermeshed in y-like fashion or in y-shaped fashion or in the form of a tuning fork.

29. The method as claimed in claim 20, comprising:

forming the trench structures in a manner proceeding from the surface region of the semiconductor material region essentially in a first extension direction (C), which runs perpendicular to the surface region of the semiconductor material region, into the semiconductor material region.

30. The method as claimed in claim 29, comprising:

forming the field electrode devices of the electrode arrangement as a stringing together of field electrode devices in the first extension direction in the interior of the trench structure.

31. The method as claimed in claim 20, comprising:

forming the trench structures essentially in a second extension direction, which runs parallel to the surface region of the semiconductor material region, in the semiconductor material region.

32. The method as claimed in claim 20, comprising:

forming the field electrode device in potential-free fashion or in floating fashion.

33. The method as claimed in claim 20, comprising:

forming a further electrode device, and in particular a control electrode device or a gate electrode device, in the interior of the trench structure in a manner facing the surface region of the semiconductor material region and in a manner spatially separated and electrically insulated from the electrode arrangement of the plurality of field electrode devices by the insulation region and from the wall region of the trench structure, from the bottom region of the trench structure and/or from the semiconductor material region.

34. The method as claimed in claim 33, comprising:

forming the further electrode device such that it is at a fixed electrical potential, in particular at source potential.

35. The method as claimed in claim 20, comprising:

forming the trench structure semiconductor device as a device or as a combination of devices from the group consisting of the group consisting of a FET, a MOSFET, a trench transistor, a field plate transistor, a vertical transistor, a vertical trench transistor, an IGBT device, a p-channel transistor, a bipolar transistor, a diode device and a Schottky diode device.

36. The method as claimed in claim 20, comprising:

forming a pillar region doped oppositely to the doping of the surroundings in the semiconductor material region and outside the trench structure and spatially at a distance from the latter, proceeding from the surface region of the semiconductor material region, the pillar region extending into the interior of the semiconductor material region, in particular in the form of a p-type pillar.

37. The method as claimed in claim 20, comprising:

forming pairs of spatially directly adjacent field electrode devices which, in a common interface region, adjoin one another and are opposite one another, relative to one another, in a targeted manner with differing degrees of pairwise electrical coupling or capacitance between the field electrode devices of the pairs of spatially directly adjacent field electrode devices which, in a common interface region, adjoin one another and are opposite one another, with respect to one another, in particular by means of a correspondingly targeted variation of the thickness of the insulation provided between the field electrode devices.

38. The method as claimed claim 20, comprising:

forming the field electrode devices such that they are electrically connected to one another via zener diodes or in high-impedance fashion in the trench structure or in an edge region.

39. The method as claimed in claim 20, wherein the sequence of method processes comprising the following processes is performed singly or multiply:

a process of deposition of an electrode layer, in particular of polysilicon, with a thickness which is less than half of the width of the remaining trench opening or trench width, if appropriate or in particular reduced by double the thickness of an insulator or oxide to be formed later, if these are deposited, in the case of oxidation approximately the single thickness suffices, and to such an extent such that the remaining trench structure is filled in its lower region and, in its upper region, only the trench sidewall and also the wafer surface are lined;

a process of filling the trench with an auxiliary layer which is etched selectively with respect to the electrode layer and serves as an etching mask with regard to the electrode layer;

a process of etching back the auxiliary layer in the trench structure as far as a defined height or depth; and

a of isotropically etching the electrode layer with the auxiliary layer as masking.

40. The method as claimed in claim 39, comprising the sequence of processes furthermore has:

a process of removing the auxiliary layer; and

a process of introducing an insulator, the last process of introducing an insulator in particular being obviated in each case when the sequence is performed multiply.

41. The method as claimed in claim 39, comprising using a photoresist, a polysilicon, a multilayer system, in particular comprising oxide, nitride and/or polysilicon, as auxiliary layer or for the auxiliary layer.

42. The method as claimed in claim 20, comprising:

forming a multilayer system as or for a field electrode device, in which multilayer system material layers, in particular polysilicon layers, which are formed differently, in particular are doped differently, and can therefore be etched at different etching rates with the same etching medium, are used and formed.

43. A method for producing a trench structure semiconductor device, comprising:

forming a semiconductor region with a surface region is formed;

forming at least one trench structure with a wall region and a bottom region is formed in the semiconductor material region;

forming a plurality of structure elements in the interior of the trench structure; and

wherein the sequence of method processes comprising the following processes is performed singly or multiply;

depositing of a material layer for a structure element, in particular of polysilicon, with a thickness which is less than half of the width of the remaining trench opening or trench width, if appropriate or in particular reduced by double the thickness of an insulator or oxide to be formed later, if these are deposited, in the case of oxidation approximately the single thickness suffices, and to such an extent such that the remaining trench structure is filled in its lower region and, in its upper region, only the trench sidewall and also the wafer surface are lined;

filling the trench with an auxiliary layer which is etched selectively with respect to the material layer for a structure element and serves as an etching mask with regard to the material layer for a structure element;

etching back the auxiliary layer in the trench structure as far as a defined height or depth;

isotropically etching the material layer for a structure element with the auxiliary layer as masking.

44. The method as claimed in claim 43, comprising the sequence of processes furthermore has:

removing the auxiliary layer; and

introducing an insulator, the last step of introducing an insulator in particular being obviated in each case when the sequence is performed multiply.

45. The method as claimed in claim 43, comprising:

using a photoresist, a polysilicon, a multilayer system, in particular comprising oxide, nitride and/or polysilicon, as auxiliary layer or for the auxiliary layer.

46. A trench structure semiconductor device, comprising:

a semiconductor material region with a surface region;

means for providing at least one trench structure with a wall region and a bottom region in the semiconductor material region;

means for providing a plurality of field electrode devices are formed in the interior of the trench structure means as an electrode arrangement in a manner spaced apart and electrically insulated from one another and from the wall region of the trench structure by an insulation region;

spatially directly adjacent and mutually adjoining field electrode device means with an enlarged common interface region with an insulation material in between; and

a stronger capacitive electrical coupling or greater capacitance of directly adjacent and mutually adjoining field electrode device means is thereby formed in comparison with substantially planar and/or smooth conditions.