Semiconductor device and semiconductor device manufacturing method

• US 20070126063A1
• Filed: 11/17/2006
• Published: 06/07/2007
• Est. Priority Date: 11/30/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aoyama, Tomonori
• Granted Patent: US 7,858,524 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.

Claims

1. A semiconductor device manufacturing method comprising:

forming a gate insulation film on a semiconductor substrate;

depositing a gate electrode material on the gate insulation film;

depositing a mask material on the gate electrode material;

shaping the mask material into a gate electrode pattern;

processing the gate electrode material into the gate electrode pattern using the shaped mask material as a mask;

forming a spacer on the side surface of the processed gate electrode material;

depositing an interlayer insulation film on the gate electrode material and on the semiconductor substrate;

polishing the interlayer insulation film until the upper surface of the mask material is exposed;

exposing the upper surface of the gate electrode material in a p-type MISFET forming-region by selectively removing the mask material in the p-type MISFET forming-region;

depositing a first metal film on the gate electrode material in the p-type MISFET forming-region;

siliciding the gate electrode material in the p-type MISFET forming-region by reacting the gate electrode material with the first metal film (a first silicidation);

exposing the upper surface of the gate electrode material in an n-type MISFET forming-region by removing the mask material in the n-type MISFET forming-region;

depositing a second metal film on the respective gate electrode materials of a p-type MISFET and an n-type MISFET; and

siliciding the respective gate electrode materials in the p-type MISFET and the n-type MISFET by reacting the respective gate electrode materials with the second metal film (a second silicidation).

2. The semiconductor device manufacturing method according to claim 1, wherein

a metal content ratio in the gate electrode of the p-type MISFET after the second silicidation is higher than that of the n-type MISFET after the second silicidation.

3. The semiconductor device manufacturing method according to claim 1, wherein

the first metal film and the second metal film are made of nickel.

4. The semiconductor device manufacturing method according to claim 3, wherein

a ratio of nickel content in the gate electrode of the p-type MISFET after the second silicidation is higher than that of the n-type MISFET after the second silicidation.

5. The semiconductor device manufacturing method according to claim 1, wherein the thickness of the first metal film is 1.1 to 1.2 times that of the gate electrode material in the p-type MISFET forming-region before the first silicidation.

6. The semiconductor device manufacturing method according to claim 1, wherein the thickness of the second metal film is 0.5 to 0.7 times that of the gate electrode material in the n-type MISFET forming-region before the second silicidation.

7. The semiconductor device manufacturing method according to claim 5, wherein the thickness of the second metal film is 0.5 to 0.7 times that of the gate electrode material in the n-type MISFET forming-region before the second silicidation.

8. The semiconductor device manufacturing method according to claim 1, wherein the thickness of the first metal film is 0.5 to 0.7 times that of the gate electrode material in the p-type MISFET forming-region before the first silicidation.

9. The semiconductor device manufacturing method according to claim 8, wherein the thickness of the second metal film is 0.5 to 0.7 times that of the gate electrode material in the n-type MISFET forming-region before the second silicidation.

10. The semiconductor device manufacturing method according to claim 1, further comprising:

introducing an n-type impurity to the gate electrode material in the n-type MISFET forming-region after depositing the gate electrode material.

11. A semiconductor device manufacturing method comprising:

forming a gate insulation film on a semiconductor substrate;

depositing a gate electrode material on the gate insulation film;

depositing a mask material on the gate electrode material;

shaping the mask material into a gate electrode pattern;

processing the gate electrode material into the gate electrode pattern using the shaped mask material as a mask;

forming a spacer on the side surface of the processed gate electrode material;

depositing an interlayer insulation film on the gate electrode material and on the semiconductor substrate;

polishing the interlayer insulation film until the upper surface of the mask material is exposed;

exposing the upper surface of the gate electrode material in a p-type MISFET forming-region by selectively removing the mask material in the p-type MISFET forming-region;

etching an upper potion of the gate electrode of the p-type MISFET forming-region;

exposing the upper surface of the gate electrode material in an n-type MISFET forming-region by removing the mask material in the n-type MISFET forming-region;

depositing a metal film on the respective gate electrode materials of a p-type MISFET and an n-type MISFET; and

siliciding the respective gate electrode materials in the p-type MISFET and the n-type MISFET by reacting the respective gate electrode materials with the metal film.

12. The semiconductor device manufacturing method according to claim 11, wherein

a ratio of metal content in the gate electrode of the p-type MISFET after the silicidation is higher than that of the n-type MISFET after the silicidation.

13. The semiconductor device manufacturing method according to claim 11, wherein

the metal film is made of nickel.

14. The semiconductor device manufacturing method according to claim 13, wherein

a ratio of nickel content in the gate electrode of the p-type MISFET after the silicidation is higher than that of the n-type MISFET after the silicidation.

15. The semiconductor device manufacturing method according to claim 11, wherein the thickness of the gate electrode material in the p-type MISFET forming-region before the silicidation is 0.3 to 0.5 times that of the gate electrode material in the n-type MISFET forming-region before the silicidation.

16. The semiconductor device manufacturing method according to claim 11, wherein the thickness of the metal film is 1.1 to 1.2 times that of the gate electrode material in the p-type MISFET forming-region before the silicidation.

17. The semiconductor device manufacturing method according to claim 15, wherein the thickness of the metal film is 1.1 to 1.2 times that of the gate electrode material in the p-type MISFET forming-region before the silicidation.

18. The semiconductor device manufacturing method according to claim 11, wherein the thickness of the gate electrode material in the p-type MISFET forming-region before the silicidation is 0.2 to 0.3 times that of the gate electrode material in the n-type MISFET forming-region before the silicidation.

19. The semiconductor device manufacturing method according to claim 18, wherein the thickness of the metal film is 1.5 to 2 times that of the gate electrode material in the p-type MISFET forming-region before the silicidation.

20. A semiconductor device comprising:

a semiconductor substrate;

a gate insulation film formed on the semiconductor substrate;

a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and

a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.