Angled implantation for removal of thin film layers

• US 20070126067A1
• Filed: 12/01/2005
• Published: 06/07/2007
• Est. Priority Date: 12/01/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack, Metz, Matthew, Brask, Justin, Hattendorf, Michael, Sandford, Justin
• Granted Patent: US 7,595,248 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a gate dielectric layer on the substrate, the gate dielectric layer having a length;

a gate electrode on the gate dielectric layer, the gate electrode having a gate length adjacent the gate dielectric layer, the gate electrode having reverse-tapered sidewalls so the gate electrode has an intermediate length further from the gate dielectric layer than the gate length, the intermediate length being greater than the gate length; and

wherein the length of the gate dielectric layer is between about 120% and about 85% of the gate length.

2. The device of claim 1, wherein at least a portion of the gate electrode sidewalls has a sidewall angle between the gate electrode sidewalls and a top surface of the substrate, the sidewall angle being between about eighty-five degrees and about seventy-five degrees.

3. The device of claim 1, wherein the gate electrode includes a work function metal gate layer comprising a first metal and a second metal gate layer comprising a second metal different than the first metal on the work function metal gate layer.

4. The device of claim 3, wherein the work function metal gate layer is conformal to the bottom and sidewalls and has a thickness between about 50 angstroms and about 100 angstroms.

5. The device of claim 1, wherein the length of the gate dielectric layer is between about 105% and about 97% of the gate length.

6. The device of claim 1, wherein the gate length is between about 18 nanometers and about 22 nanometers and the length of the gate dielectric layer is between about 23.2 nanometers and about 17.4 nanometers.

7. The device of claim 1, wherein the gate dielectric layer has a footing less than or equal to about six angstroms on each side.

8. The device of claim 1, wherein the gate dielectric layer has an undercut less than or equal to about three angstroms on each side.

9. A method, comprising:

forming a blanket dielectric layer on a substrate;

forming a gate electrode on the blanket high-k dielectric layer, an exposed portion of the blanket high-k dielectric layer being adjacent side walls of the gate electrode;

implanting ions into the exposed portion of the blanket high-k dielectric layer, the ions being implanted at an angle less than or equal to about 85 degrees to a top surface of the substrate; and

etching the exposed implanted portion to remove substantially all the exposed implanted portion and leave behind a gate dielectric layer.

10. The method of claim 9, wherein forming the gate electrode comprises:

forming a blanket gate electrode layer on a substrate; and

removing portions of the blanket gate electrode layer to leave behind a gate electrode with a gate length adjacent the blanket dielectric layer, the gate electrode having reverse-tapered sidewalls so the gate electrode has an intermediate length further from the gate dielectric layer than the gate length, the intermediate length being greater than the gate length.

11. The method of claim 10, further comprising:

forming, after forming the gate electrode and the gate dielectric layer, spacers adjacent the gate electrode sidewalls;

removing the gate electrode to leave behind a trench between the spacers; and

forming a replacement gate electrode in the trench.

12. The method of claim 11, wherein forming a replacement gate electrode in the trench comprises forming a first metal gate electrode layer, the first metal gate electrode layer being conformal to a bottom of the trench and side walls of the trench.

13. The method of claim 12, wherein the first metal gate electrode layer does not completely fill the trench and wherein forming a replacement gate electrode in the trench further comprises forming a second gate electrode layer on the first metal gate electrode layer in the trench.

14. The method of claim 10, wherein at least a portion of each of the gate electrode sidewalls has a sidewall angle between the gate electrode sidewalls and a top surface of the substrate, the sidewall angle being between about eighty-five degrees and about seventy-five degrees.

15. The method of claim 14, wherein the ions are implanted at an angle between about that of the sidewall angle and about two degrees less than the sidewall angle.

16. The method of claim 9, wherein at least a portion of the gate electrode sidewalls has a sidewall angle between the gate electrode sidewalls and the substrate and wherein implanting ions comprises:

performing a first ion implantation process, during which ions are implanted at an angle between about that of a first sidewall angle of a first gate electrode sidewall and about two degrees less than the first sidewall angle; and

performing a second ion implantation process after the first ion implantation process, during which ions are implanted at an angle between about that of a second sidewall angle of a second gate electrode sidewall opposite the first gate electrode sidewall and about two degrees less than the second sidewall angle.

17. A device, comprising:

a substrate;

a gate dielectric layer on the substrate, the gate dielectric layer having a length;

a gate electrode on the gate dielectric layer, the gate electrode having a gate length adjacent the gate dielectric layer, the gate electrode having reverse-tapered sidewalls, at least a portion of the gate electrode sidewalls has a sidewall angle between the gate electrode sidewalls and a top surface of the substrate, the sidewall angle being less than about eighty-five degrees; and

wherein the length of the gate dielectric layer is between about twelve angstroms greater than the gate length and about six angstroms less than the gate length.

18. The device of claim 17, wherein the gate length is less than about twenty-five nanometers.

19. The device of claim 17, wherein the length of the gate dielectric layer is between about 110% and about 95% of the gate length.

20. The device of claim 17, wherein the length of the gate dielectric layer is between about 104% and about 98% of the gate length.