Adaptable Detection Threshold for RFID Tags and Chips
First Claim
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1. A dual threshold circuit of a Radio Frequency Identification (RFID) tag, comprising:
- a first circuit operable to derive an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;
a second circuit operable to generate two digital outputs from the unfiltered input using two distinct decision thresholds; and
a selection circuit operable to generate a filtered output by selecting one of the digital outputs.
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Abstract
RFID tags, tag circuits, and methods are provided that reduce at least in part the distortion to received wireless signals, which is caused by interference in the environment. Two or more thresholds are used to digitize the received signal implemented by two or more demodulators. Multiple low pass and digital filters may be implemented with the demodulators, allowing removal of narrow pulses caused by the interference and reduction of beat tone amplitude.
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Citations
70 Claims
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1. A dual threshold circuit of a Radio Frequency Identification (RFID) tag, comprising:
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a first circuit operable to derive an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;
a second circuit operable to generate two digital outputs from the unfiltered input using two distinct decision thresholds; and
a selection circuit operable to generate a filtered output by selecting one of the digital outputs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for a circuit of an RFID tag, comprising:
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deriving an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;
generating two digital outputs from the unfiltered input using two distinct decision thresholds;
generating a filtered output by selecting one of the digital outputs; and
performing an operation responsive to the filtered output. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A method comprising:
- providing schematic-type inputs for the purpose of preparing a layout that embodies the inputs, in which, if the layout is incorporated in a tapeout file that is used by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit for use in an RFID tag having an antenna will result on the wafer according to the inputs, comprising;
a first and a second antenna pads that can be coupled to the antenna; and
a component that includes;
a first circuit operable to derive an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;
a second circuit for generating two digital outputs from the unfiltered input using two distinct decision thresholds; and
a selection circuit for generating a filtered output by selecting one of the digital outputs. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
- providing schematic-type inputs for the purpose of preparing a layout that embodies the inputs, in which, if the layout is incorporated in a tapeout file that is used by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit for use in an RFID tag having an antenna will result on the wafer according to the inputs, comprising;
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61. An article comprising a machine-readable memory containing thereon instructions which, if executed by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit for use in an RFID tag having an antenna will result on the wafer, comprising:
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a first and a second antenna pads that can be coupled to the antenna; and
a component that includes;
a first circuit operable to derive an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;
a second circuit for generating two digital outputs from the unfiltered input using two distinct decision thresholds; and
a selection circuit for generating a filtered output by selecting one of the digital outputs. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70)
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Specification