Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same

• US 20070127299A1
• Filed: 01/31/2007
• Published: 06/07/2007
• Est. Priority Date: 07/25/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Atsushi Nakagawa, Hiroyuki Takahashi
• Inventors: Takahashi, Hiroyuki, Nakagawa, Atsushi
• Granted Patent: US 7,397,710 B2
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes .“H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF. As described here, the NFETs (14, 7, 24) is kept OFF in the other time period than when needed, in order to reduce the power consumption.

Claims

1. An internal voltage level control circuit for controlling an activation and an inactivation of an internal voltage generating circuit which generates an internal voltage from an external power voltage,

wherein the internal voltage is compared to at least one of a first predetermined voltage and a second predetermined voltage that define a predetermined voltage range,

wherein when the internal voltage is within the predetermined voltage range, the internal voltage generating circuit is inactivated, and

wherein the internal voltage generating circuit includes a boost circuit for boosting the external power voltage, wherein the boost circuit is controlled based on at least one of the first predetermined voltage and the second predetermined voltage.

2. The internal voltage level control circuit according to claim 1, wherein the internal voltage generating circuit includes a circuit for dropping the external power voltage.

3. The internal voltage level control circuit according to claim 1, wherein when the internal voltage is outside the predetermined voltage range, the internal voltage generating circuit is activated.

4. The internal voltage level control circuit according to claim 1, further comprising:

a differential amplifier receiving an input of an internal signal having a voltage level based on the internal voltage and an input of a reference voltage signal having a voltage level that is at least one of the first predetermined voltage and the second predetermined voltage.

5. An internal voltage level control circuit, comprising:

a comparator which compares an internal voltage to at least one of a first reference voltage and a second reference voltage that define a reference voltage range;

an output control circuit which applies an external voltage to an output of the comparator when the comparator is inactivated; and

an internal voltage generator that generates the internal voltage, wherein the internal voltage generator includes a boost circuit for boosting the external voltage, wherein the boost circuit is controlled based on at least one of the first reference voltage and the second reference voltage.

6. The internal voltage level control circuit according to claim 5, wherein the internal voltage generating circuit includes a circuit for dropping the external voltage.

7. The internal voltage level control circuit according to claim 5, wherein when the internal voltage is outside the reference voltage range, the internal voltage generating circuit is activated.

8. The internal voltage level control circuit according to claim 5, wherein when the internal voltage is within the reference voltage range, the internal voltage generating circuit is inactivated and the comparison operation is discontinued.

9. The internal voltage level control circuit according to claim 5, further comprising:

a differential amplifier receiving an input of an internal signal having a voltage level based on the internal voltage and an input of a reference voltage signal having a voltage level that is at least one of the first reference voltage and the second reference voltage.

10. A semiconductor memory device, comprising:

an internal voltage generating circuit that generates an internal voltage from an external voltage; and

an internal voltage level control circuit for comparing the internal voltage to at least one of a first reference voltage and a second reference voltage that define a reference voltage range and for controlling an activation and an inactivation of the internal voltage generating circuit based on a comparison result, wherein when the internal voltage is within the reference voltage range, the internal voltage generating circuit is inactivated, and

wherein the internal voltage generating circuit includes a boost circuit for boosting the external voltage, wherein the boost circuit is controlled based on at least one of the first reference voltage and the second reference voltage.

11. The semiconductor memory device according to claim 10, wherein the internal voltage generating circuit includes a circuit for dropping the external voltage.

12. The internal voltage level control circuit according to claim 10, wherein when the internal voltage is outside the reference voltage range, the internal voltage generating circuit is activated.

13. The semiconductor memory device according to claim 10, further comprising:

a differential amplifier receiving an input of an internal signal having a voltage level based on the internal voltage and an input of a reference voltage signal having a voltage level that is at least one of the first reference voltage and the second reference voltage.

14. The semiconductor memory device according to claim 10, further comprising:

a memory cell array coupled to the internal voltage generating circuit, wherein the internal voltage generating circuit supplies the internal voltage to the memory cell array.

15. The semiconductor memory device according to claim 10, wherein the semiconductor memory device is formed over a semiconductor substrate, and the semiconductor memory device includes a back bias generating circuit for generating, from the internal voltage, a back bias voltage which is lower than a ground level and supplied to the semiconductor substrate

16. The semiconductor memory device according to claim 10, wherein the internal voltage level control circuit includes:

a comparator which compares the internal voltage to at least one of the first reference voltage and the second reference voltage; and

an output control circuit which applies the external voltage to an output of the comparator when the comparator is inactivated.