Memory module and register with minimized routing path

• US 20070127304A1
• Filed: 12/04/2006
• Published: 06/07/2007
• Est. Priority Date: 12/07/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Young-Jun, Ahn, Young-Man, Park, Sung-Joo, Yoon, Chil-Nam
• Granted Patent: US 7,652,949 B2
• Time in Patent Office: Days
• US Class Current: 365/230.10
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory module includes a first memory group including a plurality of memory devices, a second memory group including a less number of memory devices with respect to the memory devices in the first memory group, a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group, a first signal line configured to transfer the command/address signal to the first memory group, and a second signal line configured to transfer the delayed command/address signal to the second memory group.

Claims

1. A register comprising:

a first latch circuit configured to temporarily store a command/address signal;

a second latch circuit configured to temporarily store the command/address signal; and

a clock supply circuit configured to generate a first clock signal that is provided to the first latch circuit, and a second clock signal that is delayed with respect to the first clock signal and provided to the second latch circuit, wherein the first latch circuit outputs the command/address signal in synchronization with the first clock signal, and the second latch circuit outputs the command/address signal in synchronization with the second clock signal.

2. The register of claim 1, wherein the first latch circuit and the second latch circuit each comprises a plurality of D-type flip-flops.

3. The register of claim 1, further comprising:

a first output buffer configured to buffer the command/address signal outputted from the first latch circuit; and

a second output buffer configured to buffer the command/address signal outputted from the second latch circuit.

4. The register of claim 1, wherein the clock supply circuit comprises:

a first path configured to receive an external clock signal to provide the first clock signal to the first latch circuit; and

a second path configured to receive the external clock signal to provide the second clock signal to the second latch circuit.

5. The register of claim 4, wherein the first path comprises a first clock buffer configured to receive the external clock signal to output the first clock signal, and

the second path comprises a second clock buffer configured to receive the external clock signal to output the second clock signal and a delay circuit configured to delay the second clock signal.

6. The register of claim 4, wherein the external clock signal corresponds to a differential signal.

7. The register of claim 1, wherein the register has a configuration of one input terminal and two output terminals configured to receive one command/address signal and output two command/address signals.

8. A memory module comprising:

a first memory group including a plurality of memory devices;

a second memory group including a number of memory devices less than the number of the memory devices in the first memory group;

a register configured to provide a command/address signal to the first memory group and a delayed command/address signal to the second memory group;

a first signal line configured to transfer the command/address signal to the first memory group; and

a second signal line configured to transfer the delayed command/address signal to the second memory group.

9. The memory module of claim 8, wherein the second signal line is shorter than the first signal line.

10. The memory module of claim 8, wherein the register comprises:

a first latch circuit configured to temporarily store the command/address signal;

a second latch circuit configured to temporarily store the command/address signal; and

a clock supply circuit configured to generate a first clock signal that is provided to the first latch circuit, and a second clock signal that is delayed with respect to the first clock signal and provided to the second latch circuit, wherein the first latch circuit outputs the command/address signal in synchronization with the first clock signal, and the second latch circuit outputs the delayed command/address signal in synchronization with the second clock signal.

11. The memory module of claim 10, wherein the first latch circuit and the second latch circuit each comprises a plurality of D-type flip-flops.

12. The memory module of claim 10, wherein the register further comprises:

a first output buffer configured to buffer the command/address signal outputted from the first latch circuit; and

a second output buffer configured to buffer the delayed command/address signal outputted from the second latch circuit.

13. The memory module of claim 10, wherein the clock supply circuit comprises:

a first path configured to receive an external clock signal to provide the first clock signal to the first latch circuit; and

a second path configured to receive the external clock signal to provide the second clock signal to the second latch circuit.

14. The memory module of claim 13, wherein the first path comprises a first clock buffer configured to receive the external clock signal to output the first clock signal, and

the second path comprises a second clock buffer configured to receive the external clock signal to output the second clock signal, and a first delay circuit configured to delay the second clock signal.

15. The memory module of claim 14, wherein the first path further comprises a second delay circuit configured to delay the first clock signal.

16. The memory module of claim 14, wherein the external clock signal corresponds to a differential signal.

17. A memory system comprising:

a memory module which comprises;

a first memory group including a plurality of memory devices;

a second memory group including a number of memory devices less than the number of the memory devices in the first memory group;

a register configured to receive a command/address signal from the exterior and configured to provide the command/address signal to the first memory group and a delayed command/address signal to the second memory group;

a first signal line configured to transfer the command/address signal to the first memory group; and

a second signal line configured to transfer the delayed command/address signal to the second memory group; and

a memory controller configured to provide the command/address signal from the exterior to the register.

18. The memory system of claim 17, wherein the second signal line is shorter than the first signal line.

19. The memory system of claim 17, wherein the register comprises:

a first latch circuit configured to temporarily store a command/address signal;

a second latch circuit configured to temporarily store the command/address signal; and

a clock supply circuit configured to generate a first clock signal that is provided to the first latch circuit, and a second clock signal that is delayed with respect to the first clock signal and provided to the second latch circuit, wherein the first latch circuit outputs the command/address signal in synchronization with the first clock signal, and the second latch circuit outputs the delayed command/address signal in synchronization with the second clock signal.

20. The memory system of claim 19, wherein the first latch circuit and the second latch circuit each comprises a plurality of D-type flip-flops.

21. The memory system of claim 19, wherein the register further comprises:

a first output buffer configured to buffer the command/address signal outputted from the first latch circuit; and

a second output buffer configured to buffer the delayed command/address signal outputted from the second latch circuit.

22. The memory system of claim 19, wherein the clock supply circuit comprises:

a first path configured to receive an external clock signal to provide the first clock signal to the first latch circuit; and

a second path configured to receive the external clock signal to provide the second clock signal to the second latch circuit.

23. The memory system of claim 22, wherein the first path comprises a first clock buffer configured to receive the external clock signal to output the first clock signal, and

the second path comprises a second clock buffer configured to receive the external clock signal to output the second clock signal, and a first delay circuit configured to delay the second clock signal.

24. The memory system of claim 23, wherein the first path further comprises a second delay circuit configured to delay the first clock signal.

25. The memory system of claim 23, wherein the external clock signal corresponds to a differential signal.