Time stamping events for fractions of a clock cycle

• US 20070127318A1
• Filed: 12/02/2005
• Published: 06/07/2007
• Est. Priority Date: 12/02/2005
• Status: Active Grant

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Srikantam, Vamsi, Fernandez, Andrew, Vook, Dietrich
• Granted Patent: US 7,339,853 B2
• Time in Patent Office: Days
• US Class Current: 368/110
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals based on a clock phase at which the event-in signal was received. A decoder receives the event signals and outputs an event-out signal and a time stamp that represents the phase at which the event-in signal was detected. By time stamping the event-in signal to a phase division, the time stamping circuit detects event signals that occur at a rate faster than the clock cycle.

Claims

1. A time stamping circuit, comprising:

two or more detection circuits arranged to receive an event-in signal and to generate an event signal based on a phase of a clock cycle at which the event-in signal is detected; and

a decoder in electrical communication with the two or more detection circuits, the decoder outputs an event-out signal and at least one bit representing the phase of the clock cycle at which the event-in signal was detected, wherein the at least one bit is based on the event signals received from the two or more detection circuits.

2. A time stamping circuit as defined in claim 1, where in the two or more of detection circuits comprise a one or more of detection elements.

3. A time stamping circuit as defined in claim 2, wherein at least one detection element is one of a flip-flop or a latch.

4. A time stamping circuit as defined in claim 2, wherein at least one detection element in the detection circuit receives a clock having a predetermined phase and generates the event signal if the event-in signal is detected at the predetermined phase of the clock.

5. A time stamping circuit as defined in claim 4, wherein one or more other detection elements are arranged such that an elapsed time between receiving the event-in signal and providing the event signal to the decoder is different for each detection circuit.

6. A time stamping circuit as defined in claim 5, wherein at least one detection element outputs the event signal at a predetermined phase such that the event signal is output at a fraction of a full clock cycle.

7. A time stamping circuit as defined in claim 2, wherein at least one detection element outputs the event signal such that the event signal moves from one clock domain to another clock domain.

8. A time stamping circuit as defined in claim 2, wherein at least one detection circuit, comprising two or more detection elements, moves the event signal from a first clock domain in which the event-in signal was detected to a second clock domain in which the event signal is sent to the decoder.

9. A time stamping circuit as defined in claim 8, wherein there is a delay between generation of a first event signal from a first detection element and the generation of a second event signal from a second detection element.

10. A time stamping circuit as defined in claim 9, wherein the delay allows for at least one of set-up times, hold-times, or propagation delays.

11. A time stamping circuit as defined in claim 1, wherein the two or more of detection circuits forms an array of the size N by M, wherein N is a number of detection circuits and M is a number of detection elements in each detection circuit.

12. A time stamping circuit as defined in claim 11, wherein the number of detection circuits N equals a number of phase divisions available for the clock cycle.

13. A time stamping circuit as defined in claim 1, further comprising:

two or more input circuits that receive first and second inputs from one of the detection circuits and outputs a single cycle event signal based on the first and second inputs, wherein the single cycle event signal being output at a predetermined time; and

wherein the decoder identifies the phase in which the event-in signal was detected based on the single cycle event signals received from the two or more input circuits.

14. A time stamping circuit as defined in claim 13, wherein the decoder outputs at least one bit representing the identified phase at which the event-in signal was detected.

15. A time stamping circuit, comprising:

a detection circuit including two or more detection elements, each detection element arranged to receive an event-in signal and output an event signal based on a phase of a clock cycle at which the event-in signal is received; and

a decoder in electrical communication with each detection element, the decoder outputs an event-out signal and at least one bit representing the phase at which the event-in signal is detected, wherein the one bit is based on the event signals received from the detection elements.

16. A time stamping circuit as defined in claim 15, wherein at least one detection element is one of a flip-flop or a latch.

17. A time stamping circuit as defined in claim 15, wherein at least one detection element in the detection circuit receives a clock having a predetermined phase and outputs the event signal if the event-in signal is detected at the predetermined phase of the clock.

18. A time stamping circuit as defined in claim 17, wherein the detection element receives the clock as a data input.

19. A time stamping circuit as defined in claim 15, wherein the number of detection elements equals a number of phase divisions available for the clock cycle.

20. A time stamping circuit as defined in claim 15, wherein the decoder identifies the phase when the event signal was received based on the event signals received from the two or more detection elements, wherein the decoder identifies the phase asa predetermined time.

21. A time stamping circuit as defined in claim 20, wherein the decoder outputs at least two bits representing the determined phase at which the event signal was detected.

22. A method for time stamping an event signal, comprising:

receiving an event-in signal;

detecting a phase of a clock cycle during which the event-in signal was received; and

outputting an event-out signal and at least one bit representing the phase at which the event-in signal was detected.

23. A method for time stamping as defined in claim 22, wherein detecting comprises:

receiving the event-in signal and a clock having a predetermined phase at one or more detection elements; and

generating an event signal at one or more detection elements if the event-in signal is detected at the predetermined phase of the clock.

24. A method for time stamping as defined in claim 23, wherein detecting further comprises:

sending the event signal to one or more other detection elements in one or more detection circuits such that an elapsed time between receiving the event-in signal and providing the event signal to a decoder differs between the one or more detection circuits.

25. A method for time stamping as defined in claim 22, wherein outputting comprises:

receiving one or more event signals from one or more detection elements;

identifying a phase at which the event-in signal is detected based on the event signals; and

generating at least one bit representing the determined phase.