Data transfer operations and buffer memories

• US 20070127484A1
• Filed: 11/29/2006
• Published: 06/07/2007
• Est. Priority Date: 12/02/2005
• Status: Abandoned Application

• Current Assignee: Dialogic, Inc. (Enghouse Systems Limited)
• Original Assignee: Dialogic, Inc. (Enghouse Systems Limited)
• Inventors: Rau, Frank
• Application Number:
  US11/605,887
• Publication Number:
  US 20070127484A1
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: G06F 13/1631 through address comparison
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload

Abstract

A method where a datastream is received via one bus, and then is temporarily stored in a buffer memory. The datastream includes overhead data and payload data. The payload data is transmitted via a second bus. The overhead information includes information about the amount of subsequent payload data and may additionally include other information. The method extracts the information about the amount of payload data and other optional information, if any, from the received data stream and according to a reception of a complete message or a certain type of overhead information, the controlling logic of the second bus transmits or raises a request to optimally transmit the received message or parts thereof via the second bus to reduce latency for the transaction.

Claims

1. A method for delivering a datastream with payload data and overhead information, the method comprising the steps of:

(a) extracting payload length information from the overhead information;

(b) storing at least the payload data in a temporal storage buffer;

(c) determining an address in the temporal storage buffer for a current write location for a last data word of the payload data;

(d) copying the address into a first address register;

(e) marking the first address register as valid;

(f) comparing the address of the first address register with a current read location of the temporal storage buffer; and

(g) if the comparison between the entry of the first address register marked as valid and the current read location of the temporal storage buffer is not equal, setting a request to indicate that a transaction is waiting in the temporal storage buffer.

2. The method of claim 1, wherein the overhead information is at a beginning of the datastream and further comprising the step of checking the datastream for integrity based upon error checking information embedded in the datastream.

3. The method of claim 1, further comprising the steps of:

receiving the first data stream via a first bus; and

propagating the received information via a second bus, which may be different from or the same as the first bus.

4. The method of claim 1, wherein the temporal storage buffer utilizes first-in-first-out functionality and buffer controlling logic generates one or more watermark signals based on a fill level of the temporal storage buffer.

5. The method of claim 1, further comprising the steps of:

embedding the payload length information in the overhead information of the datastream, wherein the datastream includes a plurality of data words;

varying an amount of payload that is transmitted depending on a value of a transmission-length field in the overhead information;

receiving the datastream; and

transmitting the payload data of the temporal storage buffer upon grant of the request.

6. The method of claim 1, further comprising the steps of:

clearing the request and marking the address register as invalid, if the comparison between the address of the first address register and the current read location of the temporal storage buffer is equal; and

determining the address of the current write location upon storing a last data word in the temporal storage buffer.

7. The method of claim 1, further comprising the steps of:

setting a request when at least one address register of an array of a plurality of address registers is marked as valid;

comparing the current read location with all active address registers;

marking the corresponding entry as invalid if the comparison detects an equal entry; and

clearing the request when there are no active entries.

8. The method of claim 1, wherein a single controller operates a plurality of temporal storage buffers to accomplish steps (a)-(g) for each temporal storage buffer.

9. A method for reducing latency in a communication system, the method comprising the steps of:

receiving a datastream via a first bus, wherein the datastream includes payload data and overhead information;

storing at least the payload data of the datastream temporarily in a buffer memory;

raising a request to transmit at least the payload data of the datastream via a second bus according to the overhead information; and

transmitting the payload data via the second bus upon a grant of the request.

10. The method of claim 9, further comprising the steps of:

receiving a second datastream, wherein the second datastream includes payload data and overhead information and is a different size than the first datastream;

storing at least a portion of the second datastream temporarily in the buffer memory;

raising a request to transmit at least a portion of the second datastream via the second bus according to the respective overhead information; and

transmitting the portion of the second datastream via the second bus upon a grant of the request.

11. The method of claim 9, wherein the data stream further includes error detecting and error correcting information for maintaining the integrity of the payload data, and the overhead information includes one or more dedicated control signals such that a priority flag is set to expedite transmission of the payload data, wherein the transmission is processed by a special port number with priority by using non-serial and/or serial buses.

12. The method of claim 9, further comprising the steps of raising a look-ahead request based upon a predefined dataword in the datastream and using a logical Or operation on the look-ahead request and the request.

13. The method of claim 9, further comprising the step of raising the request at least one bit before a last dataword of the payload data is received.

14. A system for efficiently using a shared bus comprising:

a) a motherboard having a memory for storing an instruction set and a processor in communication with the memory for executing the instruction set; and

b) a controller card operatively connected to the motherboard for receiving a datastream including overhead data indicating an amount of payload data and the payload data, the controller card having a system controller for governing the operation of the controller card and temporal buffer circuitry operatively connected to the system controller for receiving the datastream,

wherein based on the overhead data, the system controller signals the temporal buffer circuitry to receive all of the payload data for a corresponding transaction and raises a request to the motherboard to further transmit all of the payload data temporarily stored in the buffer memory via the shared bus.

15. A system as recited in claim 14, wherein when all the payload data of the transaction is read out of the temporal buffer circuitry, the system controller releases the request for accessing the shared bus.

16. A system as recited in claim 14, wherein if another complete transaction is stored in the temporal buffer circuitry, the request stays active.

17. A system as recited in claim 14, wherein the system controller transmits optimal length bursts if the payload data is of an excessive length.

18. A system as recited in claim 14, wherein the system controller includes memory storing an instruction set, a processor in communication with the memory for executing the instruction set, DMA circuitry, an arbiter, logic circuitry and interfacing circuitry.

19. A system as recited in claim 14, wherein the controller card uses a look-ahead request, which is logically Ored with the request.

20. A system for efficiently transmitting a datastream on a shared bus comprising:

a) a controller card having a memory for storing an instruction set and a processor in communication with the memory for executing the instruction set;

b) temporal buffer circuitry operatively connected to the controller card for receiving the datastream; and

c) controller circuitry operatively connected to the controller card for receiving the datastream including overhead data indicating an amount of payload data and the payload data, wherein the controller circuitry governs operation of the temporal buffer circuitry,

wherein based on the overhead data, the controller card signals the temporal buffer circuitry to receive all of the payload data for a corresponding transaction and raises a request to further transmit all of the payload data temporarily stored in the buffer memory via the shared bus.

21. A system as recited in claim 20, wherein the controller circuitry is integral with the controller card, the datastream includes a transmission-length field in the overhead data and the controller card raises the request at least one bit before a last dataword of the payload data is received.