Data transfer operations and buffer memories
First Claim
1. A method for delivering a datastream with payload data and overhead information, the method comprising the steps of:
- (a) extracting payload length information from the overhead information;
(b) storing at least the payload data in a temporal storage buffer;
(c) determining an address in the temporal storage buffer for a current write location for a last data word of the payload data;
(d) copying the address into a first address register;
(e) marking the first address register as valid;
(f) comparing the address of the first address register with a current read location of the temporal storage buffer; and
(g) if the comparison between the entry of the first address register marked as valid and the current read location of the temporal storage buffer is not equal, setting a request to indicate that a transaction is waiting in the temporal storage buffer.
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Accused Products
Abstract
A method where a datastream is received via one bus, and then is temporarily stored in a buffer memory. The datastream includes overhead data and payload data. The payload data is transmitted via a second bus. The overhead information includes information about the amount of subsequent payload data and may additionally include other information. The method extracts the information about the amount of payload data and other optional information, if any, from the received data stream and according to a reception of a complete message or a certain type of overhead information, the controlling logic of the second bus transmits or raises a request to optimally transmit the received message or parts thereof via the second bus to reduce latency for the transaction.
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Citations
21 Claims
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1. A method for delivering a datastream with payload data and overhead information, the method comprising the steps of:
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(a) extracting payload length information from the overhead information;
(b) storing at least the payload data in a temporal storage buffer;
(c) determining an address in the temporal storage buffer for a current write location for a last data word of the payload data;
(d) copying the address into a first address register;
(e) marking the first address register as valid;
(f) comparing the address of the first address register with a current read location of the temporal storage buffer; and
(g) if the comparison between the entry of the first address register marked as valid and the current read location of the temporal storage buffer is not equal, setting a request to indicate that a transaction is waiting in the temporal storage buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for reducing latency in a communication system, the method comprising the steps of:
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receiving a datastream via a first bus, wherein the datastream includes payload data and overhead information;
storing at least the payload data of the datastream temporarily in a buffer memory;
raising a request to transmit at least the payload data of the datastream via a second bus according to the overhead information; and
transmitting the payload data via the second bus upon a grant of the request. - View Dependent Claims (10, 11, 12, 13)
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14. A system for efficiently using a shared bus comprising:
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a) a motherboard having a memory for storing an instruction set and a processor in communication with the memory for executing the instruction set; and
b) a controller card operatively connected to the motherboard for receiving a datastream including overhead data indicating an amount of payload data and the payload data, the controller card having a system controller for governing the operation of the controller card and temporal buffer circuitry operatively connected to the system controller for receiving the datastream, wherein based on the overhead data, the system controller signals the temporal buffer circuitry to receive all of the payload data for a corresponding transaction and raises a request to the motherboard to further transmit all of the payload data temporarily stored in the buffer memory via the shared bus. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A system for efficiently transmitting a datastream on a shared bus comprising:
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a) a controller card having a memory for storing an instruction set and a processor in communication with the memory for executing the instruction set;
b) temporal buffer circuitry operatively connected to the controller card for receiving the datastream; and
c) controller circuitry operatively connected to the controller card for receiving the datastream including overhead data indicating an amount of payload data and the payload data, wherein the controller circuitry governs operation of the temporal buffer circuitry, wherein based on the overhead data, the controller card signals the temporal buffer circuitry to receive all of the payload data for a corresponding transaction and raises a request to further transmit all of the payload data temporarily stored in the buffer memory via the shared bus. - View Dependent Claims (21)
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Specification