SEMICONDUCTOR HAVING ENHANCED CARBON DOPING

• US 20070127536A1
• Filed: 02/02/2007
• Published: 06/07/2007
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Johnson, Ralph
• Granted Patent: US 7,856,041 B2
• Time in Patent Office: Days
• US Class Current: 372/50.110
• CPC Class Codes: H01S 5/04257 having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/18308 having a special structure for lateral current or light confinement
• CPC Class Codes: H01S 5/18311 using selective oxidation
• CPC Class Codes: H01S 5/1833 with more than one structure
• CPC Class Codes: H01S 5/18341 Intra-cavity contacts
• CPC Class Codes: H01S 5/18358 containing spacer layers to adjust the phase of the light wave in the cavity
• CPC Class Codes: H01S 5/305 characterised by the doping materials used in the laser structure
• CPC Class Codes: H01S 5/3095 Tunnel junction

Abstract

Semiconductors with enhanced strain. One embodiment includes a semiconductor device. The semiconductor device may include an epitaxial structure. The epitaxial structure includes one or more semiconductor layers and dielectric layers. One or more of the layers includes a dopant including small quantities of Al and repeated delta doping during expitaxial growth to form periods where surfaces are group III rich.

Claims

1. A VCSEL comprising:

a substrate;

a bottom DBR mirror disposed on the substrate;

a first conduction layer region of a first conductivity type, the first conduction layer region coupled to the bottom DBR mirror, an active layer region disposed on the first conduction layer region, the active layer region containing quantum wells;

a doped second conduction layer region of a second conductivity type, the doped second conduction layer region coupled to the active layer region;

a top mirror coupled to the second conduction layer region; and

wherein one or more of the layers comprise a dopant including small quantities of Al and repeated delta doping.

2. The VCSEL as recited in claim 1, wherein the delta doping includes common carbon sources including CBr₄, CCl₄, and the mixed compounds CBr_xCl₄₋

x where x is an integer 0-4.

3. The VCSEL as recited in claim 1, wherein a resulting sheet resistance of the conduction layers in the second conduction layer region is about 250 ohms/square>

Rs>

100 ohms/square.

4. The VCSEL as recited in claim 1, wherein the thickness of conduction layers in the second conduction layer region is about 25 nm.

5. The VCSEL as recited in claim 1, wherein three conduction layers are included in the second conduction layer region.

6. The VCSEL as recited in claim 1, wherein the top and bottom mirrors are semiconductor mirrors.

7. The VCSEL as recited in claim 1, wherein the top and bottom mirrors are dielectric mirrors.

8. The VCSEL as recited in claim 1, wherein the VCSEL is designed to operate at wavelengths above about 1260 nm.

9. The VCSEL as recited in claim 1, wherein the VCSEL is designed to operate at wavelengths above about 830 nm.

10. A method of fabricating a VCSEL epitaxial structure including epitxial layers, the method comprising:

forming a bottom mirror on a substrate wherein forming a bottom mirror comprises forming alternating layers of materials with different indices of refraction;

forming a first conduction layer region on the bottom mirror;

forming an active layer region that contains quantum wells on the first conduction layer region;

forming a second conduction layer region on the active layer region;

forming a top mirror on the second conduction layer region; and

applying a dopant including small quantities of Al and repeated delta doping during expitaxial growth.

11. The method as recited in claim 10, wherein the delta doping includes common carbon sources including CBr₄, CCl₄, and the mixed compounds CBr_xCl₄₋

x where x is an integer 0-4.

12. The method as recited in claim 10, wherein a resulting sheet resistance of the conduction layers in the second conduction layer region is about 250 ohms/square>

Rs>

100 ohms/square.

13. The method as recited in claim 10, wherein the thickness of conduction layers in the second conduction layer region is about 25 nm.

14. The method as recited in claim 10, wherein three conduction layers are included in the second conduction layer region.

15. A semiconductor device, wherein the semiconductor comprises:

an epitaxial structure, wherein the epitaxial structure comprises one or more semiconductor layers and dielectric layers; and

wherein one or more of the layers comprises a dopant including small quantities of Al and repeated delta doping during expitaxial growth.

16. The semiconductor device of claim 15, further comprising applied strain to one or more of the layers.

17. The semiconductor device of claim 16, wherein the strain is applied using Indium (In).

18. The semiconductor device of claim 16, wherein the strain is applied using Antimony (Sb)

19. The semiconductor device of claim 15, where at least one adjacent layer has a higher valence band energy.

20. The semiconductor layer of claim 19 where at least 1 adjacent layer is strained.