Process-variation tolerant diode, standard cells including the same, tags and sensors containing the same, and methods for manufacturing the same

• US 20070128760A1
• Filed: 09/15/2006
• Published: 06/07/2007
• Est. Priority Date: 12/07/2005
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Smith, Patrick, Subramanian, Vivek
• Granted Patent: US 7,528,017 B2
• Time in Patent Office: Days
• US Class Current: 438/57
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/86 controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (V_t) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the V_t of an NMOS TFT (V_tn) and the V_t of a PMOS TFT (V_tp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Claims

1. A method of making complementary diodes, comprising:

a) forming a first patterned semiconductor layer on a substrate, the first patterned semiconductor layer having a first conductivity type;

b) forming a second patterned semiconductor layer on the substrate, the second patterned semiconductor layer having a second conductivity type;

c) forming a patterned insulator layer over the first and second patterned semiconductor layers and the substrate; and

d) forming a first patterned metal layer on the patterned insulator layer and in electrical contact with the first and second patterned semiconductor layers.

2. The method of claim 1, wherein forming the first patterned semiconductor layer comprises printing or laser writing a first semiconductor composition, and forming the second patterned semiconductor layer comprises printing or laser writing a second semiconductor composition.

3. The method of claim 1, wherein at least one of the first and second semiconductor compositions comprises an ink containing a silane and/or silicon nanoparticles.

4. The method of claim 1, wherein forming the first and second patterned semiconductor layers comprises printing one or more semiconductor ink compositions containing a silane and/or silicon nanoparticles.

5. The method of claim 1, wherein forming the first patterned metal layer comprises printing a first metal composition.

6. The method of claim 1, further comprising, after said first and second patterned semiconductor layer forming steps, the step of forming a patterned gate structure over the first patterned semiconductor layer.

7. The method of claim 6, wherein the patterned gate structure comprises a second patterned metal layer on a patterned gate dielectric layer.

8. The method of claim 6, wherein forming the patterned gate structure comprises printing or laser writing a second metal composition on a gate dielectric layer.

9. The method of claim 1, further comprising, after said first patterned semiconductor layer forming step, the step of forming a third patterned semiconductor layer over the first patterned semiconductor layer.

10. The method of claim 1, wherein forming the third patterned semiconductor layer comprises printing or laser writing a third semiconductor composition on the first patterned semiconductor layer.

11. The method of claim 10, wherein forming the third patterned semiconductor layer comprises printing a second semiconductor ink composition containing a second silane and/or silicon nanoparticles.

12. The method of claim 10, wherein the third patterned semiconductor layer differs from the first patterned semiconductor layer.

13. A circuit, comprising:

a) an NMOS diode having at least one printed or laser-written structure therein;

b) a PMOS diode having at least one printed or laser-written structure therein; and

c) a metal wire connecting the NMOS diode to the PMOS diode.

14. The circuit of claim 13, wherein said NMOS diode comprises an NMOS thin film transistor (TFT) and said PMOS diode comprises a PMOS TFT.

15. The circuit of claim 13, wherein said NMOS diode comprises a first Schottky diode having a printed or laser-written n-doped semiconductor layer, and said PMOS diode comprises a second Schottky diode having a printed or laser-written p-doped semiconductor layer.

16. The circuit of claim 13, wherein said metal wire comprises a printed metal wire.

17. The circuit of claim 13, wherein said NMOS diode comprises an n-doped semiconductor layer, and said PMOS diode comprises a p-doped semiconductor layer, each of said n-doped and p-doped semiconductor layers having a substantially uniform dopant distribution along substantially the entire thickness thereof while in an amorphous phase.

18. A clamp circuit, comprising:

a) first and second nodes; and

b) at least one circuit of claim 13, in series between said first and second nodes.

19. The clamp circuit of claim 18, comprising a plurality of the circuits of claim 9, in series between said first and second nodes.

20. The clamp circuit of claim 18, further comprising a shunt transistor having a gate receiving an output from one of said NMOS and PMOS diodes, a source coupled to one of said first and second nodes and a drain coupled to the other of said first and second nodes.

21. The clamp circuit of claim 18, further comprising a resistor coupled between one of said first and second nodes and the gate of the shunt transistor.

22. An alternating current clamp circuit, comprising:

a) a first circuit of claim 20, coupled between said first and second nodes; and

b) a second circuit of claim 20, coupled between said first and second nodes in parallel with said first circuit, but with a polarity opposite of said first circuit.

23. The alternating current clamp circuit of claim 22, wherein the first and second nodes comprise a differential signal transmission line.

24. A high frequency (HF), ultrahigh frequency (UHF), radio frequency identification (RFID) or electronic article surveillance (EAS) device, comprising:

a) an antenna and/or inductor;

b) a rectifier, configured to convert a radio frequency signal received by said antenna and/or inductor into power;

c) the alternating current clamp circuit of claim 22, configured to limit a voltage of the radio frequency signal; and

d) logic configured to recover a clock signal from the radio frequency signal and generate an identification signal.

25. The device of claim 24, wherein said antenna and/or inductor comprises first and second coils, respectively coupled to first and second rectifier input nodes.

26. The device of claim 25, wherein the alternating current clamp circuit is coupled between said first and second rectifier input nodes.

27. A method of limiting a first voltage on a first node, comprising:

a) receiving a signal on the first node; and

b) clamping the signal to a second voltage on a second node by passing current through the circuit of claim 13 when a difference between the first and second voltages exceeds a predetermined value.