TCP/IP offload network interface device

• US 20070130356A1
• Filed: 01/23/2007
• Published: 06/07/2007
• Est. Priority Date: 04/27/1998
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Boucher, Laurence, Craft, Peter, Starr, Daryl, Blightman, Stephen, Higgen, David, Philbrick, Clive
• Granted Patent: US 7,664,868 B2
• Time in Patent Office: Days
• US Class Current: 709/230
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: H04L 45/66 Layer 2 routing, e.g. in Ethernet based MAN's
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/193 at the transport layer, e.g. TCP related
• CPC Class Codes: H04L 47/36 by determining packet size, e.g. maximum transfer unit [MTU]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9052 with buffers of different sizes
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9068 in the network interface card
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 61/10 : of different types
• CPC Class Codes: H04L 67/10 : in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 67/34 : involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 67/62 : Establishing a time schedule for servicing the requests
• CPC Class Codes: H04L 67/63 : Routing a service request depending on the request content or context
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 : Protocol engines
• CPC Class Codes: H04L 69/16 : Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 : Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 : involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 : In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/166 : IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/22 : Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 : Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 : Network security protocols

Abstract

An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes

Claims

1. A system for receiving a packet from a network and for performing protocol processing on the packet, the packet being communicated to the system via a network connection, the system comprising:

a device coupled to the network, the device including hardware receive circuitry adapted for accelerating the protocol processing of the packet by the system; and

a protocol processing stack configured for passing control of the network connection to the device, wherein the device and the protocol processing stack are arranged such that the packet is generally processed by the device instead of the protocol processing stack when the device is maintaining the network connection, wherein microcode instructions are downloaded into the device prior to the device receiving the packet, the device executing the microcode instructions in carrying out the protocol processing on the packet.

2. The system of claim 1, wherein the system has a fast-path and a slow-path, wherein the packet includes a TCP header, and wherein the packet is processed by the fast-path such that the protocol processing stack performs substantially no TCP protocol processing on the packet.

3. The system of claim 1, wherein the packet includes a TCP header, and wherein the hardware receive circuitry performs TCP checksum validation.

4. The system of claim 1, wherein the hardware receive circuitry performs header validation.

5. The system of claim 1, wherein the network connection is a TCP connection.

6. The system of claim 1, wherein the network connection is identified by a TCP source port, a TCP destination port, an IP source address, and an IP destination address.

7. The system of claim 1, wherein the device includes a processor, the processor and the hardware receive circuitry together performing fast-path processing on the packet.

8. The system of claim 1, wherein the hardware receive circuitry is a receive sequencer.

9. The system of claim 1, wherein the device comprises a processor, the processor executing the microcode instructions.

10. The system of claim 1, wherein the system includes an integrated circuit, the integrated circuit comprising the hardware receive circuitry, a processor, a memory, and a plurality of MACs, the microcode instructions being executed by the processor.

11. A method, comprising:

downloading microcode instructions onto a TCP/IP offload device and storing the microcode instructions on the TCP/IP offload device, the TCP/IP offload device comprising hardware receive circuitry and a processor, the hardware receive circuitry and the processor being disposed on an integrated circuit;

receiving a network communication onto the TCP/IP offload device, the network communication including a TCP header;

using the hardware receive circuitry to perform initial TCP protocol processing on the network communication;

executing the microcode instructions on the processor such that the processor performs, subsequent TCP protocol processing on the network communication, the processor generating processed network communication information; and

processing the processed network communication information on a device, the device executing a protocol stack, the device and the protocol stack performing session layer processing on the processed network communication information, the device and protocol stack performing substantially no TCP protocol processing on the processed network communication information.

12. The method of claim 11, wherein the initial TCP protocol processing is TCP checksum validation.

13. The method of claim 11, wherein the hardware receive circuitry includes a fly-by state-machine.

14. A method of performing TCP layer protocol processing and IP layer protocol processing, the method comprising:

downloading microcode instructions onto a TCP/IP offload device and storing the microcode instructions on the TCP/IP offload device, the TCP/IP offload device comprising hardware receive circuitry and a processor, the hardware receive circuitry and the processor being disposed on a single integrated circuit;

receiving a network communication onto the TCP/IP offload device, the network communication including a TCP checksum and an IP checksum;

using the hardware receive circuitry to validate the TCP checksum and to validate the IP checksum; and

executing the microcode instructions on the processor such that the processor performs TCP layer protocol processing and IP layer protocol processing on the network communication; and

sending data from the network communication to a device but not sending any TCP header of the network communication to the device.

15. The method of claim 14, wherein the executing of the microcode instructions on the processor results in processed network information, the processed network information being further processed by the device executing a protocol stack, the protocol stack including a session layer protocol processing layer, the protocol stack performing session layer protocol processing on the processed network information, the protocol stack performing substantially no TCP protocol processing and substantially no IP protocol processing on the processed network information.

16. The method of claim 15, wherein the TCP header has a length, the hardware receive circuitry validating the length of the TCP header.

17. The method of claim 14, wherein the hardware receive circuitry includes a fly-by state machine.

18. The method of claim 14, wherein the network communication includes a session layer header, the session layer header indicating one of a plurality of session layer protocols, the hardware receive circuitry examining the network communication and outputting an indication of the session layer protocol.

19. The method of claim 14, wherein the hardware receive circuitry classifies the network communication into one of a plurality of classes.

20. The method of claim 19, wherein one of the classes is a fast-path class, and wherein another of the classes is a slow-path-class.