Method of making an electronic device cooling system

• US 20070131645A1
• Filed: 12/09/2005
• Published: 06/14/2007
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Kapusta, Christopher, Goodwin, Stacey, Balch, Ernest, Matthew Durocher, Kevin
• Granted Patent: US 7,427,566 B2
• Time in Patent Office: Days
• US Class Current: 216/2
• CPC Class Codes: F28F 3/12 Elements constructed in the shape of a hollow panel, e.g. with channels F28D1/02, F28D1/03 take precedence
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241

Abstract

A method is provided. The method includes forming a conductive layer on an inner surface of a substrate and providing a sacrificial layer over the conductive layer. The method includes forming a plurality of channels in the sacrificial layer and plating the sacrificial layer to substantially fill the plurality of channels with a plating material comprising conducting material. The method also includes etching the sacrificial layer to form a conducting structure having fins where conducting material remains separated by microchannels where the sacrificial layer is etched.

Claims

1. A method comprising,

forming a conductive layer on an inner surface of a substrate;

providing a sacrificial layer over the conductive layer;

forming a plurality of channels in the sacrificial layer;

plating the sacrificial layer to substantially fill the plurality of channels with a plating material comprising conducting material; and

etching the sacrificial layer to form a conducting structure having fins where conducting material remains separated by microchannels where the sacrificial layer is etched.

2. The method of claim 1, the substrate comprising silicon, silicon carbide, aluminum nitride, alumina, gallium nitride or a combination thereof.

3. The method of claim 1, further comprising mounting a power electronic device proximate to an outer surface of the substrate.

4. The method of claim 1, wherein forming the conductive layer comprises sputtering of a conducting material on the inner surface, or disposing the conducting material on the inner surface using an adhesive.

5. The method of claim 4, the adhesive comprising an epoxy, a thermoplastic material, a thermosetting material or a combination thereof.

6. The method of claim 1, wherein the conductive layer has a thickness of less than about 300 microns.

7. The method of claim 1, the sacrificial layer comprising silicon.

8. The method of claim 1, wherein the sacrificial layer has a thickness of less than about 400 microns.

9. The method of claim 1, wherein the plurality of channels are formed by etching the sacrificial layer.

10. The method of claim 1, wherein the plurality of channels are formed by sawing the sacrificial layer.

11. The method of claim 1, wherein the microchannels have a width of less than about 200 microns.

12. The method of claim 11, wherein the microchannels have a width of from about 100 microns to about 200 microns.

13. The method of claim 1, wherein the microchannels are less than about 400 microns deep.

14. The method of claim 13, wherein the microchannels are about 300 microns to about 400 microns deep.

15. The method of claim 1, wherein the microchannels have an aspect ratio of width to height of about 1:

2 to about 1;

3.

16. The method of claim 1, wherein plating the sacrificial layer comprises electroplating.

17. The method of claim 1 further comprising providing an inlet manifold in fluid communication with the microchannels to introduce a coolant in the microchannels, and providing an outlet manifold in fluid communication with the microchannels to exhaust the coolant from the microchannels.

18. The method of claim 17, further comprising providing an inlet plenum to introduce the coolant to the inlet manifold, and providing an outlet plenum to exhaust the coolant from the outlet manifold.

19. The method of claim 1, further comprising forming an additional conductive layer over the conductive layer.

20. A method comprising:

forming a copper layer on an inner surface of a substrate;

forming a sacrificial layer comprising silicon over the copper layer;

forming a plurality of channels in the sacrificial layer;

plating the sacrificial layer with copper to substantially fill the plurality of channels; and

etching the sacrificial layer to leave a copper structure having microchannels where the sacrificial layer has been etched, wherein an aspect ratio of width to height of the microchannels is in a range of about 1;

2 to about 1;

3.

21. A method comprising,

disposing a layer of a first thermally conductive material on a surface of a substrate;

disposing a sacrificial layer over the thermally conductive material;

forming a plurality of channels in the sacrificial layer;

plating the sacrificial layer to substantially fill the plurality of channels with a plating material comprising a second thermally conductive material; and

removing remaining portions of the sacrificial layer to form a thermally conducting structure having fins made of the second conductive material separated by microchannels where the remaining sacrificial layer was removed.

22. The method of claim 21, wherein the first and second thermally conductive materials are the same material.

23. The method of claim 21, wherein the plurality of channels are formed by etching the sacrificial layer.

24. The method of claim 21, wherein the plurality of channels are formed by sawing the sacrificial layer.