VERTICAL TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF

• US 20070131998A1
• Filed: 02/26/2007
• Published: 06/14/2007
• Est. Priority Date: 11/03/2005
• Status: Abandoned Application

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Lin, Shian-Jyh, Shih, Neng-Tai, Chen, Sheng-Tsung
• Application Number:
  US11/679,087
• Publication Number:
  US 20070131998A1
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

Claims

1-11. -11. (canceled)

12. A method of fabricating a vertical transistor device, comprising:

providing a substrate;

forming a deep trench in the substrate;

forming a capacitor inside a lower portion of the deep trench;

forming a conductive structure on the capacitor inside the deep trench;

growing an epitaxial layer on a surface of the substrate, the epitaxial layer having an epitaxial sidewall region; and

forming a vertical gate structure on the conductive structure and adjacent to the epitaxial sidewall region.

13. The method of claim 12, wherein forming the deep trench comprises:

depositing a pad layer on the substrate;

patterning the pad layer; and

etching the substrate, using the pad layer as a mask, to form the deep trench.

14. The method of claim 12, wherein forming the capacitor comprises:

forming a buried bottom electrode in a lower portion of the deep trench in the substrate;

forming a node dielectric layer on a bottom and a sidewall of the deep trench, the node dielectric layer adjacent to the buried bottom electrode; and

forming a top electrode inside the deep trench, the top electrode surrounded by the node dielectric layer.

15. The method of claim 12, wherein forming the conductive structure comprises:

forming a collar dielectric on a sidewall of the deep trench and above the capacitor;

forming a conductive layer inside the deep trench, wherein the conductive layer is adjacent to the capacitor and comprises a lower portion surrounded by the collar dielectric; and

forming a buried strap on the collar dielectric, adjacent to a top portion of the conductive layer.

16. The method of claim 12, further comprising forming a trench top insulator on the conductive structure and adjacent to a top surface of the substrate.

17. The method of claim 16, wherein the trench top insulator is formed by depositing a silicon oxide layer using high density plasma chemical vapor deposition.

18. The method of claim 12, further comprising forming a buried strap isolation in the substrate and between two adjacent deep trenches.

19. The method of claim 18, wherein the buried strap isolation is formed by implanting a dopant using self-aligned ion implantation.

20. The method of claim 19, wherein the dopant comprises boron or indium.

21. The method of claim 12, wherein the epitaxial layer comprises selective epitaxial silicon layer formed by epitaxial growth.

22. The method of claim 12, wherein forming the vertical gate structure comprises:

forming a gate dielectric on the epitaxial sidewall region;

forming a gate electrode on the trench top insulator and next to the gate dielectric; and

respectively forming a source region and a drain region in a top portion and a bottom portion of the epitaxial sidewall region;

wherein the vertical gate structure comprises a channel region having a channel length extending from the source region to the drain region.

23. The method of claim 22, wherein the gate dielectric comprises silicon oxide formed by thermal oxidation.

24. The method of claim 22, wherein the gate electrode comprises polysilicon, titanium nitride, tungsten nitride, tungsten silicide, tungsten or metal compound formed by physical vapor deposition or chemical vapor deposition.