Unipolar resistance random access memory (RRAM) device and vertically stacked architecture
First Claim
Patent Images
1. A memory structure comprising:
- vertically-stacked first and second memory pillars separated by a bit line or word line, the first pillar including, a first diode having a first direction of current flow;
a first unipolar re-writable resistance random access memory (RRAM) stack formed below the first diode and above a bit line or word line separating the first and second pillars;
the second pillar including, a second diode positioned to have a second direction of current flow being opposite to the first direction of current flow; and
a second unipolar re-writable RRAM stack formed below the second diode.
1 Assignment
0 Petitions
Accused Products
Abstract
One embodiment of the present invention includes a low-cost unipolar rewritable variable-resistance memory device, made of cross-point arrays of memory cells, vertically stacked on top of one another and compatible with a polycrystalline silicon diode.
-
Citations
41 Claims
-
1. A memory structure comprising:
-
vertically-stacked first and second memory pillars separated by a bit line or word line, the first pillar including, a first diode having a first direction of current flow;
a first unipolar re-writable resistance random access memory (RRAM) stack formed below the first diode and above a bit line or word line separating the first and second pillars;
the second pillar including, a second diode positioned to have a second direction of current flow being opposite to the first direction of current flow; and
a second unipolar re-writable RRAM stack formed below the second diode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A 3-dimensional memory arrangement made of memory trees positioned on top of semiconductor control circuitry comprising:
-
at least one row of memory trees including a first type of memory tree;
each tree having one tree trunk connecting a corresponding memory tree to the semiconductor control circuitry and each tree having a plurality of branches with at least one branch in each of a plurality of layers defining word lines in a plurality of layers, the word lines of a tree sharing a common vertical connection through the trunk of the tree to the semiconductor control circuitry;
a plurality of bit lines in at least one layer formed substantially perpendicular to the word lines, each of the plurality of bit lines independently connected to the semiconductor control circuitry, each of the bit lines being shared by every tree in the row of memory trees; and
a plurality of unipolar re-writable memory pillars in a plurality of layers formed at the intersections of word lines and bit lines. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
33. A method of manufacturing a memory array having memory pillars comprising:
-
depositing a conducting layer;
first etching to form the first layer of bit lines or word lines;
depositing a first SiO2 layer;
performing chemical mechanical planarization (CMP);
depositing re-writable RRAM stack memory layers;
depositing diode layers to form a diode having a first direction of current flow;
second etching the deposited memory layers and diode layers;
forming a pillar;
depositing a second SiO2 layer; and
performing CMP. - View Dependent Claims (34, 35, 36, 37, 38)
-
-
39. A memory structure comprising:
a first memory pillar formed above a bit line and including, a first unipolar re-writable resistance random access memory (RRAM) stack;
a first diode having a first direction of current flow and formed above the first stack; and
a word line formed above the first memory pillar. - View Dependent Claims (40, 41)
Specification