METHOD FOR MANUFACTURING A WAFER LEVEL CHIP SCALE PACKAGE

• US 20070132108A1
• Filed: 02/21/2007
• Published: 06/14/2007
• Est. Priority Date: 10/22/2002
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Dong-Ho, LEE, Jin-Hyuk, KIM, Gu-Sung, JANG, Dong-Hyeon
• Application Number:
  US11/677,478
• Publication Number:
  US 20070132108A1
• Time in Patent Office: Days
• US Class Current: 257/780
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/02145 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]

Abstract

A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.

Claims

1. A wafer level chip scale package (CSP), comprising:

a semiconductor chip having chip pads and a passivation layer exposing chip pads;

a first patterned dielectric layer disposed on the passivation layer; and

a second patterned dielectric layer, the first and second patterned dielectric layers exposing the chip pads,

wherein the first and second patterned dielectric layers have an embossed portion comprising a concave portion and a convex portion, the concave portion exposing a portion of the first patterned dielectric layer where a ball pad is to be formed, the convex portion being formed of the second patterned dielectric layer.

2. The apparatus of claim 1, wherein the concave portion comprises a circle shape, and the convex portion comprises a ring shape and having a smaller diameter than the concave portion.

3. The apparatus of claim 1, wherein the convex portion comprises a discontinuous ring shape.

4. The apparatus of claim 1, wherein the area of the concave portion inside the convex portion is approximately equal to the area of the convex portion.