System and methods for test time outlier detection and correction in integrated circuit testing

• US 20070132477A1
• Filed: 12/28/2006
• Published: 06/14/2007
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Optimal Plus Ltd. (Emerson Electric Company)
• Original Assignee: Optimal Test Limited
• Inventors: Linde, Reed, Balog, Gil, Golan, Avi
• Granted Patent: US 7,528,622 B2
• Time in Patent Office: Days
• US Class Current: 324/762.10
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Claims

1. A method of semiconductor testing comprising:

while a test program is being applied to a semiconductor device, deciding that said device is testing too slowly and that based on a yield criterion said device is to be prevented from completing said test program; and

preventing said device from completing said test program;

wherein after said device has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

2. The method of claim 1, wherein said deciding includes:

checking whether the number of devices which tested too slowly and were previously designated for being prevented from completing said test program is less than a maximum allowed number of such devices, and

if less than said maximum, deciding that based on a yield criterion said device is to be prevented from completing said test program.

3. The method of claim 1, wherein said deciding includes:

checking whether the number of devices which passed said test program is more than a predetermined minimum desired number of passing devices; and

if more than said minimum, deciding that based on a yield criterion said device is to be prevented from completing said test program.

4. The method of claim 1, wherein said deciding includes:

checking whether the number of devices which were previously designated for being prevented from completing said test program for any reason is less than a maximum allowed number of such devices; and

if less than said maximum, deciding that based on a yield criterion said device is to be prevented from completing said test program.

5. The method of claim 1, wherein said deciding includes:

checking whether at least two conditions apply selected from a group comprising;

the number of devices which tested too slowly and were previously designated for being prevented from completing said test program is less than a maximum allowed number of such devices, the number of devices which passed said test program is more than a predetermined minimum desired number of passing devices, and the number of devices which were previously designated for being prevented from completing said test program for any reason is less than a maximum allowed number of such devices; and

if said at least two conditions apply, deciding that based on a yield criterion said device is to be prevented from completing said test program.

6. The method of claim 1, further comprising:

customizing said yield criterion based on at least one test factory condition.

7. The method of claim 6, wherein said customizing includes:

increasing a maximum number of devices allowed to be prevented from completing said test program because of testing too slowly in order to attempt to increase a number of devices on which said test program is applied in a predetermined time period.

8. The method of claim 6, wherein said customizing includes:

decreasing a maximum number of devices allowed to be prevented from completing said test program because of testing too slowly in order to attempt to increase a number of devices which pass said test program.

9. The method of claim 1, wherein said deciding includes:

recognizing that said device is testing too slowly because at least one test time for applying at least one test in said test program to said device exceeds at least one maximum test time for said at least one test.

10. The method of claim 1, wherein said deciding includes:

recognizing that said device is testing too slowly based on data relating to a plurality of tests in said test program.

11. The method of claim 1, wherein said deciding includes:

recognizing that said device is testing too slowly because said device has not completed at least one test when a maximum test time for said at least one test has elapsed.

12. The method of claim 1, wherein said deciding includes:

recognizing that said device is testing too slowly compared to at least one other device being tested in parallel.

13. The method of claim 1, wherein said test program is applied to said device at a separate time from any other device.

14. The method of claim 1, wherein said test program is applied in parallel to said device and to at least one other device in a parallel group.

15. The method of claim 1, wherein said device prevented from completing said test program is discarded.

16. The method of claim 1, wherein said device prevented from completing said test program is retested at a later time.

17. The method of claim 1, wherein said deciding includes:

recognizing that said device is testing too slowly based on a customized value for a test time parameter.

18. A method of semiconductor testing comprising:

while a test program is being applied to said semiconductor device, recognizing said semiconductor device as a candidate for test aborting because said device is testing too slowly based on a customized value for a test time parameter;

deciding whether to abort testing on said candidate; and

preventing said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one

remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

19. The method of claim 18, wherein said customized value was determined based on a sample of devices assumed to share a common response to testing with said device.

20. The method of claim 19, wherein devices are assumed to share a common response to testing based on positioning in a wafer.

21. The method of claim 19, wherein devices are assumed to share a common response to testing based on lithography exposure.

22. The method of claim 18, further comprising customizing said customized value including:

providing a value of a test time parameter derived from a sample of devices corresponding to a first time point or time period; and

deriving a new value for said test time parameter from a sample of devices corresponding to a later time point or time period, wherein said later time point or later time period is prior to said applying said test program to said device;

wherein said customized value is said new value.

23. The method of claim 18, wherein said customized value was determined based on at least one test factory condition.

24. The method of claim 23, wherein said at least one test factory condition includes at least one selected from a group comprising:

test capacity and test yield.

25. The method of claim 23, wherein said customized value is a setting for a maximum test time, further comprising:

increasing a setting for a maximum test time in order to attempt to increase a number of devices which pass said test program.

26. The method of claim 23, wherein said customized value is a setting for a maximum test time, further comprising:

decreasing a setting for a maximum test time in order to attempt to increase a number of devices on which said test program is applied in a predetermined time period.

27. The method of claim 18, wherein said deciding whether to abort is based at least partially on a yield criterion.

28. The method of claim 18, wherein said deciding includes:

deciding that said candidate should have testing aborted, as a corollary of being a candidate.

29. The method of claim 18, wherein said recognizing includes:

recognizing said device as a candidate for test aborting because at least one test time for applying at least one test in said test program to said device exceeds at least one customized maximum test time for said at least one test.

30. The method of claim 18, wherein said recognizing includes:

recognizing said device as a candidate for test aborting based on a customized value for a test time parameter relating to a plurality of tests in said test program.

31. The method of claim 18 wherein said recognizing includes:

recognizing said device as a candidate for test aborting because said device has not completed at least one test when a customized maximum test time for said at least one test has elapsed.

32. The method of claim 18, wherein said recognizing includes:

after another device in a parallel testing group including said semiconductor device has completed said test program, recognizing at that point said device as candidate for test aborting because an anticipated remaining test time for said device to complete said test program is too long based on at least one customized test time parameter value.

33. The method of claim 18, wherein said test program is applied to said device at a separate time from any other device.

34. The method of claim 18, wherein said test program is applied in parallel to said device and to at least one other device in a parallel group.

35. A method of semiconductor testing comprising:

while a test program is being applied to said semiconductor device, recognizing said semiconductor device as a candidate for test aborting because said device is testing too slowly based on data relating to a plurality of tests in said test program;

deciding whether to abort testing on said candidate; and

preventing said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

36. The method of claim 35, wherein said recognizing includes:

recognizing said device as a candidate for test aborting because at least two test times for applying at least two tests in said test program to said device exceed at least two maximum test times for said at least two tests, respectively.

37. The method of claim 35, wherein said recognizing includes:

recognizing said device as a candidate for test aborting because a test time for applying a plurality of tests in said test program to said device exceeds a maximum test time for said combination of tests.

38. The method of claim 37, wherein said plurality includes all tests in said test program.

39. The method of claim 35, wherein said recognizing includes:

recognizing said device as a candidate for test aborting because said device has not completed a plurality of tests when a maximum test time for said plurality of tests has elapsed.

40. The method of claim 39, wherein said plurality includes all tests in said test program and wherein said maximum test time is a maximum test time for completing said test program.

41. The method of claim 35, wherein said plurality of tests are consecutive.

42. The method of claim 35, wherein said plurality of tests excludes at least one test executed in said test program between two tests in said plurality.

43. The method of claim 35, wherein said recognizing includes:

after another device in a parallel testing group including said semiconductor device has completed said test program, recognizing at that point that said device is a candidate for test aborting because an anticipated remaining test time for said device to complete said test program is too long.

44. The method of claim 43, wherein said anticipated test time is too long because a summation of typical test times for all at least one remaining test in said test program exceeds a difference between a maximum test time for said test program and a typical test time for said test program.

45. The method of claim 43, wherein said recognizing at that point that said device is a candidate for test aborting includes:

looking up in a table an entry for a test which is currently being applied to said device; and

based on said entry recognizing that at that point said device as a candidate for test aborting.

46. The method of claim 35, wherein said deciding whether to abort is based at least partially on a yield criterion.

47. The method of claim 35, wherein said deciding includes:

deciding that said candidate should have testing aborted, as a corollary of being a candidate.

48. The method of claim 35, wherein said test program is applied to said device at a separate time from any other device.

49. The method of claim 35, wherein said test program is applied in parallel to said device and to at least one other device in a parallel group.

50. The method of claim 35, wherein said data includes a customized value for a test time parameter.

51. The method of claim 35, wherein said recognizing includes:

recognizing said semiconductor device as a candidate for test aborting because said device is testing too slowly based on data relating to a plurality of tests in said test program compared to at least one other device being tested in parallel.

52. A method of semiconductor testing comprising:

while a test program is being applied to a semiconductor device in parallel with at least one other semiconductor device, recognizing said semiconductor device as a candidate for test aborting because said device is testing too slowly compared to at least one other device being tested in parallel;

deciding whether to abort testing on said candidate; and

preventing said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

53. The method of claim 52, wherein said recognizing includes:

after another device in a parallel testing group including said semiconductor device has completed said test program, recognizing at that point that said device is a candidate for test aborting because an anticipated test time for said device to complete said test program is too long.

54. The method of claim 53, wherein said anticipated test time is too long because a summation of typical test times for all at least one remaining test in said test program exceeds a difference between a maximum test time for said test program and a typical test time for said test program.

55. The method of claim 53, wherein said recognizing at that point that said device is a candidate for test aborting includes:

looking up in a table an entry for a test which is currently being applied to said device; and

based on said entry recognizing that at that point said device as a candidate for test aborting.

56. The method of claim 52, wherein said test program is applied to at least one of said remaining untested semiconductor devices only after each device in a parallel testing group including said semiconductor device has completed said test program or has been prevented from completing said test program.

57. The method of claim 52, wherein said test program is applied to at least one of said remaining untested semiconductor devices by redeploying a test site being used to test said device to an untested semiconductor device within a same touchdown after said device has completed said test program or has been prevented from completing said test program.

58. The method of claim 52, wherein said preventing said candidate from completing said test program includes aborting testing on said device prior to a last device in a parallel testing group including said device completes said test program.

59. The method of claim 52, wherein at least one device in a parallel testing group including said device fails at least one test, causing said at least one device to be prevented from completing said test program, or wherein at least one device in said parallel group including said device has testing aborted because of testing too slowly and is therefore prevented from completing said test program.

60. The method of claim 52, wherein said decision is to abort and wherein said device is discarded.

61. The method of claim 52, wherein said decision is to abort and wherein said device is retested at a later time.

62. The method of claim 52, wherein said deciding includes:

recognizing that said device is a candidate for test aborting based on a customized value for a test time parameter.

63. The method of claim 52, wherein said deciding whether to abort is based at least partially on a yield criterion.

64. The method of claim 52, wherein said deciding includes:

deciding that said candidate should have testing aborted, as a corollary of being a candidate.

65. A system for semiconductor testing, comprising:

an algorithm engine, external to a tester, configured to recognize that a device is testing too slowly and that a test program should be aborted;

said algorithm engine configured to indicate to a tester to abort said test program on said semiconductor device.

66. The system of claim 65, further comprising:

a tester configured apply a said test program on said semiconductor device.

67. The system of claim 66, wherein said tester is further configured to generate monitor data, and wherein said algorithm engine is configured to recognize that said device is testing too slowly and that said test program should be aborted based on at least part of said generated monitor data.

68. The system of claim 67, wherein said tester includes at least one monitor data generator selected from a group comprising:

test time monitor, test status monitor, and yield monitor.

69. The system of claim 66, wherein said tester is further configured to apply said test program to said device in parallel with at least one other device.

70. The system of claim 66, wherein said test program includes test time limits for individual tests in said test program, and wherein said algorithm engine is configured to recognize that a device is testing too slowly even though said test limits in said test program have not been exceeded.

71. The system of claim 65, wherein said algorithm engine is configured to recognize that said device is testing too slowly and said test program should be aborted based on at least one parameter setting.

72. The system of claim 71, further comprising:

at least one selected from test program settings module, and rules and threshold settings module configured to provide said at least one parameter setting.

73. The system of claim 71, wherein said at least one parameter setting comprises at least one selected from a group comprising:

maximum test time value for a test, maximum test time value for a test program, typical test time value for a test, typical test time value for a test program, maximum number of too-slow testing devices allowed to have testing aborted, maximum test time for a plurality of tests, typical test time for a plurality of tests, and an entry in a look up table indicating whether a device undergoing a test is testing too slowly.

74. The system of claim 71, wherein a setting for one of said parameters depends on which group of semiconductor devices with an assumed common response to testing includes said semiconductor device.

75. The system of claim 71, wherein a setting for one of said parameters varies over time.

76. The system of claim 71, wherein a setting for one of said parameters depends on at least one test factory condition.

77. The system of claim 65, wherein said algorithm engine is further configured based on a received indication to proceed with evaluating or suspend evaluating whether said device is testing too slowly and said test program should be aborted.

78. The system of claim 77, further comprising:

at least one watchdog timer configured to provide said indication received by said algorithm engine.

79. The system of claim 65, wherein said algorithm engine is configured to recognize that said device is testing too slowly in comparison to at least one other device being tested in parallel.

80. A computer program product comprising a computer useable medium having computer readable program code embodied therein for semiconductor testing, the computer program product comprising:

computer readable program code for causing the computer, while a test program is being applied to a semiconductor device, to decide that said device is testing too slowly and that based on a yield criterion said device is to be prevented from completing said test program; and

computer readable program code for causing the computer to prevent said device from completing said test program;

wherein after said device has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

81. A computer program product comprising a computer useable medium having computer readable program code embodied therein for semiconductor testing, the computer program product comprising:

computer readable program code for causing the computer, while a test program is being applied to said semiconductor device, to recognize said semiconductor device as a candidate for test aborting because said device is testing too slowly based on a customized value for a test time parameter;

computer readable program code for causing the computer to decide whether to abort testing on said candidate; and

computer readable program code for causing the computer to prevent said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

82. A computer program product comprising a computer useable medium having computer readable program code embodied therein for semiconductor testing, the computer program product comprising:

computer readable program code for causing the computer while a test program is being applied to said semiconductor device, to recognize said semiconductor device as a candidate for test aborting because said device is testing too slowly based on data relating to a plurality of tests in said test program;

computer readable program code for causing the computer to decide whether to abort testing on said candidate; and

computer readable program code for causing the computer to prevent said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

83. A computer program product comprising a computer useable medium having computer readable program code embodied therein for semiconductor testing, the computer program product comprising:

computer readable program code for causing the computer, while a test program is being applied to a semiconductor device in parallel with at least one other semiconductor device, to recognize said semiconductor device as a candidate for test aborting because said device is testing too slowly compared to at least one other device being tested in parallel;

computer readable program code for causing the computer to decide whether to abort testing on said candidate; and

computer readable program code for causing the computer to prevent said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.