Four-wire signaling system

• US 20070132485A1
• Filed: 12/09/2005
• Published: 06/14/2007
• Est. Priority Date: 12/09/2005
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Alon, Elad, Pamarti, Sudhakar
• Application Number:
  US11/299,072
• Publication Number:
  US 20070132485A1
• Time in Patent Office: Days
• US Class Current: 327/18
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

A signaling device is described. The signaling device may include a group of four signal nodes, four differential receivers and a logic circuit. The group of four signal nodes may receive a sequence of data bits during a sequence of bit times. A respective differential receiver of the four differential receivers may be coupled to two respective signal nodes in the group of four signal nodes. The logic circuit may extract common-mode data from signals on the group of four signal nodes using outputs from the four differential receivers such that three data bits are received on the group of four signal nodes during each bit time of the sequence of bit times.

Claims

1. A signaling device, comprising:

a group of four signal nodes to receive a sequence of data bits during a sequence of bit times;

four differential receivers, wherein a respective differential receiver of the four differential receivers is coupled to two respective signal nodes in the group of four signal nodes; and

a logic circuit coupled to the four differential receivers, the logic circuit to extract common mode data from signals on the group of four signal nodes using outputs from the four differential receivers such that three data bits are received on the group of four signal nodes during each bit time of the sequence of bit times.

2. The device of claim 1, wherein

the four signal nodes are arranged into a first pair of signal nodes and a second pair of signal nodes;

a first differential receiver in the four differential receivers is coupled to the first pair of signal nodes and a second differential receiver in the four differential receivers is coupled to the second pair of signal nodes, and

an output from the first differential receiver corresponds to a first bit in the three data bits and an output from the second differential receiver corresponds to a second bit in the three data bits.

3. The device of claim 2, wherein a third differential receiver in the four differential receivers is coupled to a first signal node in the first pair of signal nodes and a second signal node in the second pair of signal nodes, and wherein a fourth differential receiver in the four differential receivers is coupled to a third signal node in the first pair of signal nodes and the second signal node in the second pair of signal nodes.

4. The device of claim 1, wherein

the four signal nodes are arranged into a first pair of signal nodes and a second pair of signal nodes;

and

a control signal is determined from an output of the first differential receiver and an output of the second differential receiver, and wherein the control signal is coupled to the logic circuit.

5. The device of claim 1, wherein the four differential receivers are binary receivers having a detection threshold of substantially zero.

6. The device of claim 1, wherein one or more of the four differential receivers is a multi-level receiver having at least one detection threshold that is different than 0.

7. The device of claim 1, further comprising:

a group of four signal lines coupled to the group of four signal nodes; and

a transmitter coupled to the group of four signal lines, wherein the transmitter differentially drives signals corresponding to a first bit in the three bits on a first pair of signal lines in the four signal lines, differentially drives signals corresponding to a second bit in the three bits on a second pair of signal lines in the four signal lines, and differentially drives signals corresponding to a third bit in the three bits as the common mode data on the first pair of signal lines and the second pair of signal lines.

8. The device of claim 7, wherein the transmitter includes three differential driver circuits.

9. The device of claim 8, wherein one of the three differential drivers has a substantially different output amplitude than other differential drivers.

10. The device of claim 8, wherein clock circuits for two of the three differential drivers include respective phase adjustment elements, and wherein the respective phase adjustment elements provide compensation for a timing offset between first signals on the first pair of signal lines and second signals on the second pair signal lines that is less than a bit time.

11. The device of claim 10, wherein the compensation substantially aligns the signals corresponding to the first, second and third bits.

12. The device of claim 10, wherein data input lines for the two of the three differential drivers include respective integer delay elements, the respective integer delay elements providing delays corresponding to an integer multiple of the bit time.

13. The device of claim 10, further comprising delay control logic, wherein the delay control logic adjusts the respective phase adjustment elements for one or more of the clock circuits in accordance with outputs from one or more of the four differential receivers.

14. The device of claim 7, wherein the transmitter includes at least six single-ended drivers.

15. The device of claim 14, wherein clock circuits for at least three of the single-ended drivers include respective phase adjustment elements, and wherein the respective phase adjustment elements provide compensation for timing offsets between signals on the group of four signal lines that are less than the bit time.

16. The device of claim 15, wherein data input lines for at least three of the single-ended drivers include respective integer delay elements, the respective integer delay elements providing delays corresponding to an integer multiple of the bit time.

17. The device of claim 1, wherein a first signal node and a second signal node are coupled to a first differential receiver in the four differential receivers, the second signal node and a third signal node are coupled to a second differential receiver in the four differential receivers, the third signal node and a fourth signal node are coupled to a third differential receiver in the four differential receivers, and the first signal node and the fourth signal node are coupled to a fourth differential receiver in the four differential receivers.

18. The device of claim 17, wherein outputs from two of the four differential receivers are used to determine a single one of the three bits.

19. A method of extracting common mode data, comprising:

receiving signals on a group of four signal lines; and

extracting the common mode data from the signals using four differential receivers and a logic circuit such that the signals convey three respective data bits during each bit time of a sequence of bit times.

20. The method of claim 19, further comprising determining a control signal from an output of a first differential receiver and an output of a second differential receiver, wherein the extracting the common mode data is in accordance with the control signal.

21. The method of claim 19, further comprising:

transmitting first differential signals corresponding to a first data bit on a first pair of the group of four signal lines;

transmitting second differential signals corresponding to a second data bit on a second pair of the group of four signal lines; and

transmitting third differential signals corresponding to a third data bit on the first pair of the group of four signal lines and on the second pair of the group of four signal lines.

22. The method of claim 21, further comprising compensating for a timing offset between the first differential signals and the second differential signals, wherein the timing offset is less than a data bit time.

23. A signaling device, comprising

a group of four signal nodes to receive a sequence of data bits during a sequence of bit times;

four differential receivers, wherein a respective differential receiver of the four differential receivers is coupled to two respective signal nodes in the group of four signal nodes; and

means for extracting common mode data from signals on the group of four signal nodes using outputs from the four differential receivers such that three data bits are received on the group of four signal nodes during each bit time of the sequence of bit times.

24. A computer readable medium containing data representing a circuit that includes:

a signaling receiver, comprising;

a group of four signal nodes to receive a sequence of data bits during a sequence of bit times;

four differential receivers, wherein a respective differential receiver of the four differential receivers is coupled to two respective signal nodes in the group of four signal nodes; and

a logic circuit, wherein the logic circuit extracts common mode data from signals on the group of four signal nodes using outputs from the four differential receivers such that three data bits are received on the group of four signal nodes during each bit time of the sequence of bit times.