Buffer management in vector graphics hardware

• US 20070132775A1
• Filed: 01/31/2007
• Published: 06/14/2007
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: DDEEG Microconsulting Oy (Advanced Micro Devices, Inc.)
• Inventors: Tuomi, Mika
• Granted Patent: US 8,390,634 B2
• Time in Patent Office: Days
• US Class Current: 345/568
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture

Abstract

A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.

Claims

1. A processor unit for processing vector graphics primitives, the processor unit comprising:

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel;

a first internal buffer configured to store at least one indicator bit value for each pixel; and

determination logic configured to determine whether to retrieve and to retrieve the counter value from a memory based on the indicator bit values.

2. The processor unit of claim 1, wherein the processor unit is further configured to clear said memory by resetting said indicator bit values from said first internal buffer.

3. The processor unit of claim 1, the processor unit further comprising a bus, wherein said processor is configured to receive instructions and data from said bus

4. The processor unit of claim 3, wherein in said bus is a unidirectional bus.

5. The processor unit of claim 1, further comprising:

a second internal buffer configured to store limited values for each counter,

wherein the determination logic is further configured to determine whether to retrieve the limited counter values from the second buffer.

6. The processor unit of claim 5, wherein the processor unit is further configured to clear said memory and said second internal buffer by resetting said indicator bit values from said first internal buffer.

7. The processor unit of claim 5, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has not changed.

8. The processor unit of claim 5, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has to be retrieved from an external memory.

9. The processor unit of claim 5, wherein the indicator bits of the first buffer include values for indicating a range of the second buffer from which the limited value of each counter is retrieved.

10. The processor unit of claim 1, wherein the memory is an external memory configured to store counter values for each pixel to be processed.

11. The processor unit of claim 1, wherein the memory is an internal memory configured to store counter values for each pixel to be processed.

12. The processor unit of claim 1, wherein a memory is configured to store complete counter values for each sub-pixel having a counter.

13. The processor unit of claim 1, wherein the processor unit further comprises:

an internal memory arranged to store a portion of the complete counter values.

14. The processor unit of claim 13, wherein the portion is a scan line.

15. The processor unit of claim 13, wherein the portion is a tile.

16. A processor unit for processing vector graphics primitives, the processor unit comprising:

an internal memory configured to store a portion of vector graphics primitives; and

wherein said portion of vector graphics primitives is a tile corresponding to a portion of the memory wherein said vector graphics primitives are stored.

17. The processor unit of claim 16, wherein the processor unit further comprising:

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel.

18. A handheld device, comprising:

a display;

a processing unit for processing vector graphics primitives, and including;

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel,

a first internal buffer configured to store at least one indicator bit value for each pixel,

a memory for storing data, and

determination logic configured to determine whether to retrieve and to retrieve the counter value from a memory based on the indicator bit values.

19. The handheld device of claim 18, wherein the handheld device is further configured to clear said memory by resetting said indicator bit values from said first internal buffer.

20. The handheld device of claim 18, the handheld device further comprising a bus, wherein said processing unit is configured to receive instructions and data from said bus

21. The handheld device of claim 18, wherein in said bus is a unidirectional bus.

22. The handheld device of claim 18, wherein the processing unit further comprises:

a second internal buffer configured to store limited values for each counter,

wherein the determination logic is further configured to determine whether to retrieve the limited counter values from the second buffer.

23. The handheld device of claim 22, wherein the handheld device is further configured to clear said memory and said second internal buffer by resetting said indicator bit values from said first internal buffer.

24. The handheld device of claim 22, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has not changed.

25. The handheld device of claim 22, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has to be retrieved from an external memory.

26. The handheld device of claim 22, wherein the indicator bits of the first buffer include values for indicating a range of the second buffer from which the limited value of each counter is retrieved.

27. The handheld device of claim 18, wherein the memory is an external memory configured to store counter values for each pixel to be processed.

28. The handheld device of claim 18, wherein the memory is an internal memory configured to store counter values for each pixel to be processed.

29. The handheld device of claim 18, wherein a memory is configured to store complete counter values for each sub-pixel having a counter.

30. The handheld device of claim 18, wherein the processor unit further comprises:

an internal memory arranged to store a portion of the complete counter values.

31. The handheld device of claim 30, wherein the portion is a scan line.

32. The handheld device of claim 30, wherein the portion is a tile.

33. The handheld device of claim 18, wherein the device comprises a handheld device.

34. An apparatus for processing vector graphics primitives, the apparatus comprising:

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel;

a first internal buffer configured to store at least one indicator bit value for each pixel; and

determination logic configured to determine whether to retrieve the counter value from a memory based on the indicator bit values,

wherein the apparatus is further configured to clear said memory by resetting said indicator bit values from said first internal buffer.

35. The apparatus of claim 34, wherein the apparatus further comprising a second internal buffer configured to store limited values for each counter,

wherein the determination logic is further configured to determine whether to retrieve the limited counter values from the second buffer and wherein the apparatus is further configured to clear said memory and said second internal buffer by resetting said indicator bit values from said first internal buffer.

36. The apparatus of claim 34, where in the apparatus is further comprising a unidirectional bus for receiving instructions.