Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices

• US 20070133247A1
• Filed: 11/22/2006
• Published: 06/14/2007
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kyu-Hyoun, Choi, Joo-Sun, Park, Kwang-Soo, Lee, Jae-Jun
• Granted Patent: US 7,405,949 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

Claims

1. A memory system, comprising:

first and second primary memories;

first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection;

at least one memory module having at least two of the first and second primary and first and second secondary memories;

a first connection element for connecting the memory module to a mother board; and

a second connection element for connecting at least one other of the first and second primary and first and second secondary memories to the mother board;

wherein at least one of the memories on the first memory module is coupled to at least one of the other memories.

2. The memory system of claim 1, wherein the first connection element is a connector connecting the memory module to the mother board.

3. The memory system of claim 1, wherein the second connection element comprises solder for fixedly attaching the at least one other of the first and second primary and first and second secondary memories to the mother board.

4. The memory system of claim 1, wherein the first primary memory and the second primary memory are affixed to the first memory module.

5. The memory system of claim 1, wherein the first primary memory and the first secondary memory are affixed to the first memory module.

6. The memory system of claim 1, wherein the first primary memory and the second primary memory are soldered to the mother board.

7. The memory system of claim 1, wherein the first primary memory and the first secondary memory are soldered to the mother board.

8. The memory system of claim 1, further comprising a second memory module to which at least two others of the first and second primary and first and second secondary memories are attached.

9. The memory system of claim 8, wherein the second connection element is a connector connecting the second memory module to the mother board.

10. The memory system of claim 8, further comprising a flexible conductor element connecting the first and second memory modules.

11. The memory system of claim 10, wherein the flexible conductor element carries command/address (CA) signals.

12. The memory system of claim 10, wherein the flexible conductor element carries data signals.

13. The memory system of claim 10, wherein the flexible conductor element carries command/address (CA) signals and data signals.

14. The memory system of claim 8, wherein the first primary memory and the second primary memory are affixed to the first memory module.

15. The memory system of claim 8, wherein the first primary memory and the first secondary memory are affixed to the first memory module.

16. The memory system of claim 8, wherein the first secondary memory and the second secondary memory are affixed to the second memory module.

17. The memory system of claim 8, wherein the second primary memory and the second secondary memory are affixed to the second memory module.

18. The memory system of claim 1, further comprising a controller coupled to at least one of the first and second primary memories.

19. The memory system of claim 18, wherein the controller is coupled to the at least one primary memory via a point-to-point link.

20. The memory system of claim 18, wherein the controller is coupled to the first and second primary memories via a point-to-two-point link.

21. The memory system of claim 18, wherein the controller transmits command/address (CA) signals to both of the primary memories.

22. The memory system of claim 21, wherein, during an access to one of the secondary memories, one of the primary memories repeats command/address signals from the controller to the one of the secondary memories being accessed.

23. The memory system of claim 18, wherein a first half of data being accessed is transferred to the controller by one of the primary and secondary memories, and a second half of the data being accessed is transferred to the controller by another of the primary and secondary memories.

24. The memory system of claim 18, wherein a first half of data being accessed is transferred to the controller by one of the secondary memories, and a second half of the data being accessed is transferred to the controller the other of the secondary memories.

25. A memory system, comprising:

first and second primary memories;

a controller for transmitting signals to the first and second primary memories, the signals being transmitted to the first and second memories by a point-to-two-point link.

26. The memory system of claim 26, wherein the signals comprise command/address (CA) signals.

27. The memory system of claim 26, further comprising first and second secondary memories coupled to the first and second primary memories, respectively.

28. The memory system of claim 27, wherein coupling between the primary and secondary memories comprises at lest one point-to-point connection.

29. The memory system of claim 27, further comprising:

a first memory module having at least two of the first and second primary and first and second secondary memories; and

a second memory module having at least the other two of the first and second primary and fist and second secondary memories.

30. The memory system of claim 29, further comprising a flexible conductor element connecting the first and second memory modules.

31. The memory system of claim 30, wherein the flexible conductor element carries command/address (CA) signals.

32. The memory system of claim 30, wherein the flexible conductor element carries data signals.

33. The memory system of claim 30, wherein the flexible conductor element carries command/address (CA) signals and data signals.

34. The memory system of claim 27, wherein the controller transmits command/address (CA) signals to both of the primary memories.

35. The memory system of claim 34, wherein, during an access to one of the secondary memories, one of the primary memories repeats command/address (CA) signals from the controller to the one of the secondary memories being accessed.

36. The memory system of claim 27, wherein a first half of data being accessed is transferred to the controller by one of the primary and secondary memories, and a second half of the data being accessed is transferred to the controller by another of the primary and secondary memories.

37. The memory system of claim 27, wherein a first half of data being accessed is transferred to the controller by one of the secondary memories, and a second half of the data being accessed is transferred to the controller the other of the secondary memories.