Diode-less array for one-time programmable memory

• US 20070133248A1
• Filed: 12/08/2005
• Published: 06/14/2007
• Est. Priority Date: 12/08/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Ming, Chen, Kuan, Han, Tzung, Chen, Yin
• Granted Patent: US 7,486,534 B2
• Time in Patent Office: Days
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Claims

1. A one-time programmable memory array comprising:

a first row conductor extending in a first row direction and disposed at a first elevation;

a second row conductor extending in a second row direction and disposed at a second elevation;

a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor, the column direction being different from the first and second row directions;

a dielectric layer covering at least a portion of the column conductor; and

a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

2. The one-time programmable memory array according to claim 1, wherein the dielectric layer is one of nitride and silicon dioxide.

3. The one-time programmable memory array according to claim 1, wherein the fuse link is formed of doped or undoped polysilicon.

4. The one-time programmable memory array according to claim 1, wherein the first row conductor forms a wordline and the second row conductor forms a bitline.

5. The one-time programmable memory array according to claim 1, wherein the first and second row conductors and the column conductor are formed of at least one of polysilicon, copper, aluminum, germanium, tantalum, silver, gold, nickel, chromium, tin, tungsten, zinc, titanium and indium.

6. The one-time programmable memory array according to claim 1, wherein the first row direction and the second row direction are different.

7. The one-time programmable memory array according to claim 1, wherein the first row direction and the second row direction are orthogonal with respect to each other.

8. The one-time programmable memory array according to claim 1, further comprising:

an insulator filling voids between the first and second row conductors, the fuse link and the column conductor.

9. A one-time programmable memory array comprising:

a plurality of first row conductors extending in a first row direction and disposed at a first elevation;

a plurality of second row conductors extending in a second row direction and disposed at a second elevation, the second elevation being different than the first elevation;

a plurality of column conductors extending in a column direction and disposed between adjacent pairs of the plurality of first row conductors and adjacent pairs of the plurality of second row conductors;

a plurality of dielectric layers, each of the plurality of dielectric layers covering at least a portion of each one of the plurality of column conductors; and

a plurality of fuse links, each of the plurality of fuse links being coupled between one of the plurality of column conductors and one adjacent row conductor of one of the plurality of second row conductors.

10. A method of forming one-time programmable memory array comprising:

providing an intermetal oxide base;

forming a first row conductor extending in a first row direction and disposed at a first elevation with respect to the base;

forming a second row conductor extending in a second row direction and disposed at a second elevation with respect to the base;

forming a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor, the column direction being different from the first and second row directions;

depositing a dielectric layer that covers at least a portion of the column conductor;

depositing a fuse material between the dielectric layer on the column conductor and the second row conductor; and

etching the fuse material to create fuse links that are coupled between the dielectric layer on the column conductor and the second row conductor.