Single level cell programming in a multiple level cell non-volatile memory device

• US 20070133249A1
• Filed: 12/09/2005
• Published: 06/14/2007
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie
• Granted Patent: US 7,366,013 B2
• Time in Patent Office: Days
• US Class Current: 365/100
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.

Claims

1. A method for single level programming in a multiple level cell memory device, the method comprising:

writing desired data to one of either the least significant bit or the most significant bit of the cell; and

writing the reinforcing data to the remaining bit of the cell such that a threshold voltage of the cell is adjusted to a voltage level required by the desired data.

2. The method of claim 1 and further including determining the type of data to be written.

3. The method of claim 2 wherein the type of data includes data requiring high reliability and data requiring high memory density.

4. The method of claim 1 wherein writing the reinforcing data changes the threshold voltage for the cell to the level required for the desired data.

5. The method of claim 4 wherein the desired data has a threshold voltage in a multiple level cell range of threshold voltages such that a logical one state is at the most negative of the range and a logical zero state is at the most positive of the range.

6. The method of claim 1 wherein the memory device is a NAND flash memory device.

7. The method of claim 1 and further including reading the desired data by mapping the read multiple level cell data to a single level cell data.

8. The method of claim 7 wherein a ‘

11’

state maps to a logical one state and a ‘

10’

state maps to a logical zero state.

9. A method for single level programming in a multiple level cell NAND flash memory device, the method comprising:

determining a type of data to be programmed;

writing desired data to a least significant bit of a cell; and

writing reinforcing data that changes a threshold voltage of the cell to a voltage level required by the desired data.

10. The method of claim 9 wherein writing to the least significant bit comprises writing to page 0 of the memory device.

11. The method of claim 10 wherein writing the reinforcing data comprises writing page that is not adjacent to page 0 of the memory device.

12. A method for single level programming in a multiple level cell memory device comprising memory with a least significant page and a most significant page, the method comprising:

writing desired data to either the least significant page or the most significant page of at least one memory cell; and

writing reinforcing data to the remaining page of the at least one memory cell such that the remaining page is a non-adjacent page to the previously written page of each cell and is composed of reinforcing data to the desired data.

13. The method of claim 12 wherein the most significant page is at least four pages from the least significant page.

14. The method of claim 13 wherein the most significant page is four pages from the least significant page in row zero of the single level array area and six pages from the least significant page in the remaining rows of the area.

15. A memory device comprising:

a plurality of multiple level cells formed into an array of cells; and

at least one single level cell within the array of cells that is programmed and read as a single level cell in response to a driver.

16. The device of claim 15 wherein the at least one single level cell is a plurality of cells that are dynamically chosen by the driver to store data requiring higher reliability than data stored in the multiple level cells.

17. The device of claim 15 wherein the array is a NAND flash memory array.

18. The device of claim 15 wherein programmed single level cells are comprised of threshold voltage levels that are mapped to either a logical one state or a logical zero state.

19. A flash memory device comprising:

a memory array comprising a plurality of cells that are programmable to multiple levels within a range of threshold voltages; and

control circuitry that is adapted to execute a single level programming method comprising writing desired data to one of either the least significant bit or the most significant bit of a dynamically selected cell, and writing reinforcing data to the remaining bit of the cell.

20. The device of claim 19 wherein the reinforcing data adjusts a threshold voltage level for a cell being programmed to a level consistent with the desired data.

21. The device of claim 20 wherein the desired data comprises one of a negative threshold voltage for a logical one state and a positive threshold voltage for a logical zero state.

22. The device of claim 21 wherein the logical one state is a furthest state from the logical zero state in the range of threshold voltages.

23. A memory system comprising:

a processor that generates memory signals and executes a memory driver; and

a memory device coupled to the processor and operating in response to the memory signals, the memory device comprising;

a plurality of multiple level cells formed as an array of cells; and

a control circuit that programs at least one multiple level cell in a single level format in response to the memory driver.

24. A memory module comprising:

a multiple level memory array arranged in rows and columns such that the rows comprise word lines coupled to control gates of a plurality of memory cells and the columns comprise bit lines coupled to series strings of memory cells, the memory array further arranged in memory blocks; and

control circuitry that is adapted to perform single level programming of at least one dynamically selected cell of the memory array by writing desired data to one of either a least significant bit or a most significant bit of the cell and writing reinforcing data to the remaining bit of the cell; and

a plurality of contacts configured to provide selective contact between the memory array and a host system.

25. The module of claim 24 and further including a memory controller coupled to the memory array for controlling operation of the memory device in response to the host system.

26. A method for single level programming in a multiple level cell NAND flash memory device comprising a memory array, the method comprising:

determining a type of data to be programmed;

writing either multiple level cell data or single level cell data to at least one selected cell of the array in response to the type of data;

if the type of data is indicative of high reliability, writing desired data to a first bit of a cell and writing reinforcing data to a remaining bit of the cell that changes a threshold voltage of the cell to a voltage level required by the desired data; and

if the type of data is indicative of high memory density, writing the desired data in multiple level cell manner.

27. The method of claim 26 wherein writing the desired data in a multiple level cell manner comprises programming the cell to a desired threshold voltage level with a single programming operation.

28. A memory system comprising:

a processor that generates memory signals and executes a high level memory driver and a low-level memory driver; and

a memory device coupled to the processor and operating in response to the memory signals, the memory device comprising;

a plurality of multiple level cells formed as an array of cells; and

a control circuit that programs a plurality of multiple level cells in a single level cell format in response to the high-level memory driver and the low-level memory driver.

29. The device of claim 28 wherein the reinforcing data increases a threshold voltage level for a cell being programmed to a level consistent with the desired data.

30. The device of claim 29 wherein the desired data a positive threshold voltage for a logical zero state.

31. The device of claim 28 wherein a logical one state is a furthest state from the logical zero state in the range of threshold voltages.

32. A flash memory system having a processor coupled to system memory and to a flash memory device, the system comprising:

a high-level driver that is executed by the processor and selects memory locations of the flash memory device to which data is written; and

a low-level driver, coupled to the high-level driver, that is executed by the processor to write single level cell data into multiple level cell memory locations as determined by the high-level driver in response to a type of data being written.

33. The system of claim 32 wherein the type of data comprises either high reliability data or less sensitive data.