FLASH MEMORY PROGRAMMING TO REDUCE PROGRAM DISTURB

• US 20070133294A1
• Filed: 02/15/2007
• Published: 06/14/2007
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Louie, Benjamin, Han, Jin-Man
• Granted Patent: US 7,630,236 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than V_pass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at V_pass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than V_pass in order to block the gate induced drain leakage from the array.

Claims

1. A non-volatile memory device comprising:

a memory array organized as memory blocks in which each block is comprised of a plurality of word line rows, a plurality of bit line columns, and at least one row of source select gate transistors; and

control circuitry coupled to the memory array and adapted to control programming of the memory array such that the control circuitry biases a selected word line of a memory block, coupled to a memory cell to be programmed, with a programming voltage, biases unselected word lines of the memory block with a first voltage, and biases a subset of the unselected word lines with a second voltage that is less than the first voltage.

2. The device of claim 1 wherein the programming voltage is in a range of 14V to 20V.

3. The device of claim 1 wherein the first voltage is 10V.

4. The device of claim 1 wherein the control circuitry is further adapted to control generation of a series of sequentially incrementing programming pulses having amplitudes in a range of 14V to 21V.

5. The device of claim 1 wherein the control circuitry is further adapted to bias a first bit line coupled to the memory cell at ground potential.

6. The device of claim 1 wherein the control circuitry is further adapted to bias each bit line not coupled to the non-volatile memory cell at an inhibit voltage.

7. The device of claim 6 wherein the inhibit voltage is V_CC.

8. A NAND non-volatile memory device comprising:

a memory array organized in a NAND configuration and comprising a plurality of memory blocks each block comprising a plurality of rows coupled to word lines, a plurality of columns coupled to bit lines, and a plurality of source select gate transistors; and

a memory control circuit coupled to the memory array for controlling operation of the memory array, the memory control circuit adapted to program a memory cell of a memory block by biasing a selected word line coupled to the memory cell with at least one programming pulse having an initial amplitude at a programming voltage, biasing a first unselected word line of a plurality of unselected word lines with a first voltage that is less than V_pass, and biasing the remaining unselected word lines of the memory block with V_pass.

9. The device of claim 8 wherein the at least one programming pulse has an amplitude in a range from 14V to 21V that is increased by a step voltage and V_pass is 10V.

10. The device of claim 8 wherein the first voltage is also greater than ground potential.

11. The device of claim 8 wherein the first unselected word line is closer in the array to the plurality of source select gate transistors than the selected word line.

12. The device of claim 8 wherein the first unselected wordline is adjacent to the plurality of source select gate transistors.

13. A non-volatile memory device comprising:

a memory array organized in a plurality of memory blocks each block comprising a plurality of rows coupled to word lines, a plurality of columns coupled to bit lines, and a plurality of source select gate transistors; and

a memory control circuit coupled to the memory array for controlling operation of the memory array, the memory control circuit adapted to program a memory cell of a memory block by biasing a selected wordline with a programming voltage, biasing each unselected wordline with a first voltage, and biasing a first of the plurality of source select gate lines with a second voltage that is less than the first voltage.

14. The device of claim 13 wherein the first source select gate line is adjacent to a wordline of the array.

15. The device of claim 13 wherein the memory array is a NAND flash memory array.

16. The device of claim 13 wherein the memory array is a NOR flash memory array.

17. The device of claim 13 wherein the memory control circuit is further adapted to bias, at ground potential, a first bit line that is coupled to the non-volatile memory cell, bias the remaining bit lines at an inhibit voltage, and bias a select gate drain line at an initial voltage and decrease the initial voltage to a final voltage.

18. The device of claim 17 wherein the initial voltage is V_CC and the final voltage is 1V.