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Flash with consistent latency for read operations

  • US 20070133312A1
  • Filed: 02/07/2007
  • Published: 06/14/2007
  • Est. Priority Date: 05/10/2000
  • Status: Active Grant
First Claim
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1. A synchronous DRAM (SDRAM) memory interface, comprising:

  • a pipeline buffer having an input connection and an output connection, the pipeline buffer having a plurality of selectable propagation paths to route data from the input connection to the output connection wherein each propagation path requires a predetermined number of clock cycles;

    a multiplex circuit coupled to the input of the pipeline buffer, the multiplex circuit having a plurality of inputs; and

    a plurality of SDRAM-compatible interconnects, wherein one or more interconnects of the plurality of SDRAM-compatible interconnects are coupled to the output connection of the pipeline buffer.

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