Flash with consistent latency for read operations

• US 20070133312A1
• Filed: 02/07/2007
• Published: 06/14/2007
• Est. Priority Date: 05/10/2000
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie
• Granted Patent: US 7,457,169 B2
• Time in Patent Office: Days
• US Class Current: 365/189.20
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires a predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.

Claims

1. A synchronous DRAM (SDRAM) memory interface, comprising:

a pipeline buffer having an input connection and an output connection, the pipeline buffer having a plurality of selectable propagation paths to route data from the input connection to the output connection wherein each propagation path requires a predetermined number of clock cycles;

a multiplex circuit coupled to the input of the pipeline buffer, the multiplex circuit having a plurality of inputs; and

a plurality of SDRAM-compatible interconnects, wherein one or more interconnects of the plurality of SDRAM-compatible interconnects are coupled to the output connection of the pipeline buffer.

2. The synchronous DRAM (SDRAM) memory interface of claim 1, further comprising an output data buffer circuit, wherein the output data buffer is coupled between the output connection of the pipeline buffer and the one or more interconnects of the plurality of SDRAM-compatible interconnects.

3. The synchronous DRAM (SDRAM) memory interface of claim 1, wherein the pipeline buffer has three propagation paths that can be selected to provide one, two or three clock latency during read operations.

4. The synchronous DRAM (SDRAM) memory interface of claim 1, wherein a first input of the plurality input connections of the multiplex circuit is coupled to a data register circuit.

5. The synchronous DRAM (SDRAM) memory interface of claim 4, wherein the data register circuit is one of a configuration register and a status register.

6. The synchronous DRAM (SDRAM) memory interface of claim 5, wherein the status register is adapted to provide status data and where the status data comprises:

one of an active status of a state machine, a memory array bank status, or an operation error data.

7. The synchronous DRAM (SDRAM) memory interface of claim 1, wherein a second input of the plurality of input connections of the multiplex circuit is coupled to a data read circuit of an array of memory cells.

8. A synchronous DRAM (SDRAM) memory device, comprising:

a pipeline buffer having an input connection and an output connection, the pipeline buffer having a selectable propagation to route data from the input connection to the output connection;

a multiplexer circuit for selecting a data input from a plurality of data inputs coupled to the input of the pipeline buffer; and

an output data buffer circuit coupled to the output connection of the pipeline buffer and to one or more interconnects of a plurality of SDRAM-compatible interconnects of a memory package.

9. The synchronous DRAM (SDRAM) memory device of claim 8, further comprising a data register circuit coupled to a first input of the multiplexer circuit.

10. The synchronous DRAM (SDRAM) memory device of claim 9, wherein the data register circuit comprises one of an identification register, a configuration register and a status register.

11. The synchronous DRAM (SDRAM) memory device of claim 10, wherein the status register is adapted to provide status data and where the status data comprises one of an active status of a state machine of the synchronous memory device, a memory array bank status, or an operation error data.

12. The synchronous DRAM (SDRAM) memory device of claim 8, further comprising a data read circuit coupled to a second input of the multiplexer circuit, the data read circuit adapted to output data read from a memory array of the synchronous DRAM (SDRAM) memory device.

13. The synchronous DRAM (SDRAM) memory device of claim 8, wherein the synchronous DRAM (SDRAM) memory device further comprises an array of non-volatile memory cells.

14. A method of operating a memory device, comprising:

selecting a data input from a plurality of data inputs;

selecting a propagation path of the pipeline data buffer; and

outputting the data through the selected propagation path onto external data connections from the selected data input.

15. The method of claim 14, wherein selecting a data input from a plurality of data inputs further comprises selecting a data input from a plurality of data inputs with a multiplexer circuit.

16. The method of claim 14, wherein selecting a data input from a plurality of data inputs further comprises selecting a data input from a plurality of data inputs, where at least two data inputs of the plurality of data inputs are a data register circuit and a data read circuit of an array of memory cells.

17. The method of claim 14, wherein the plurality of selectable propagation paths have a time delay of one, two and three clock cycles.

18. The method of claim 14, wherein the memory device is a synchronous memory device.

19. The method of claim 14, wherein the memory device is a flash memory device.

20. A method of operating a synchronous DRAM (SDRAM) memory device, comprising:

selecting a data input from a plurality of data inputs within the synchronous DRAM (SDRAM) memory device, wherein the data input is selected depending on a mode of operation of the synchronous DRAM (SDRAM) memory device;

adjusting latency by selecting a propagation path from a plurality of propagation paths to couple the data input to external data connections of the synchronous DRAM (SDRAM) memory device; and

outputting the data from the data input on the external data connections.

21. The method of claim 20, wherein selecting a data input from a plurality of data inputs within the synchronous DRAM (SDRAM) memory device further comprises selecting a data input from a plurality of data inputs within the synchronous DRAM (SDRAM) memory device with a multiplexer circuit.

22. The method of claim 20, wherein selecting a data input from a plurality of data inputs within the synchronous DRAM (SDRAM) memory device further comprises selecting a data input from a plurality of data inputs within the synchronous DRAM (SDRAM) memory device, where the data input of the plurality of data inputs are one of a data register circuit and a data read circuit of an array of memory cells.

23. The method of claim 20, wherein the plurality of selectable propagation paths have a time delay of one, two and three wait states.

24. The method of claim 20, wherein the synchronous DRAM (SDRAM) memory device is a synchronous DRAM (SDRAM) compatible non-volatile memory device.

25. A processing system, comprising:

a memory controller; and

a memory device coupled to the memory controller and comprising;

an array of memory cells,

a pipeline data buffer having an input connection and a data output connection, the pipeline data buffer has a plurality of selectable propagation paths to route data from the input connection to the data output connection wherein each propagation path requires a predetermined number of clock cycles, the data output connection is coupled to the memory controller via a data bus, and

a multiplex circuit coupled to the input of the pipeline data buffer, the multiplex circuit having two or more inputs.

26. The processing system of claim 25, further comprising:

a register circuit coupled to a first input of the two or more inputs of the multiplex circuit; and

a memory read circuit coupled to a second input of the two or more inputs of the multiplex circuit, the data read circuit adapted to provide data read from the array of memory cells, such that data from the register circuit and the memory read circuit propagate through the pipeline data buffer circuit using one of the plurality of selectable propagation paths.

27. The processing system of claim 25, wherein the register circuit comprises one of an identification register, a configuration register and a status register.

28. The processing system of claim 25, wherein the memory controller is a processor.

29. The processing system of claim 25, wherein the plurality of selectable propagation paths comprise one, two and three clock cycle propagation delays.

30. The processing system of claim 25, wherein the memory device is a synchronous memory device.

31. The processing system of claim 25, wherein the array of memory cells is an array of non-volatile memory cells.

32. A method of reducing memory bus contention, comprising:

selecting a data input from a plurality of data inputs with a multiplexer coupled to a pipeline buffer having a plurality of propagation paths within a memory device;

adjusting the selected data input to a selected output latency for the memory device by selecting a propagation path from the plurality of propagation paths of the pipeline buffer to couple the data input to external data connections of the memory device; and

outputting the data from the data input on the external data connections.

33. The method of claim 32, wherein the data input of the plurality of data inputs is one of a data register circuit and a data read circuit coupled to an array of memory cells.

34. The method of claim 32, wherein the plurality of selectable propagation paths have a time delay of one, two and three wait states.

35. The method of claim 32, wherein the memory device is a synchronous memory device.

36. The method of claim 32, wherein the memory device is a non-volatile memory device.

37. A synchronous memory device, comprising:

a multiplexer circuit, wherein the multiplexer circuit is adapted to select a data input from a plurality of data inputs;

a pipeline buffer having an input connection and an output connection, the pipeline buffer having two or more selectable propagation paths to route data from the input connection to the output connection, wherein the input connection is coupled to an output of the multiplex circuit; and

an output data buffer circuit coupled to the output connection of the pipeline buffer.

38. The synchronous memory device of claim 37, further comprising a data register circuit coupled to a first input of the plurality of data inputs of the multiplex circuit.

39. The synchronous memory device of claim 38, wherein the data register circuit comprises one of an identification register, a configuration register and a status register.

40. The synchronous memory device of claim 37, further comprising a data read circuit coupled to a second input of the plurality of data inputs of the multiplex circuit, the data read circuit adapted to output data read from a memory array of the synchronous memory device.

41. The synchronous memory device of claim 37, wherein the synchronous memory device is a synchronous DRAM (SDRAM) compatible memory device.

42. The synchronous memory device of claim 37, wherein the synchronous memory device is a non-volatile memory device.