A STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME

• US 20070134855A1
• Filed: 06/22/2006
• Published: 06/14/2007
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Hsieh, Kuang-Yeu, Lue, Hang-Ting
• Granted Patent: US 7,709,334 B2
• Time in Patent Office: Days
• US Class Current: 438/142
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A stacked non-volatile memory device comprises a plurality of bitline and word line layers stacked on top of each other. The bitline layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Claims

1. A method for fabricating a non-volatile memory device comprising a plurality of bitline layers and a plurality of word line layers sequentially formed on top of each other, the method comprising

forming a first bitline layer, wherein forming a first bitline layer comprises:

forming a semiconductor layer on a insulator;

patterning and etching the semiconductor layer to form a plurality of bitlines;

forming a first word line layer over the first bitline layer, wherein forming the first word line layer comprises;

sequentially forming a first trapping structure, a conducting layer and a second trapping structure; and

patterning and etching the first and second trapping structures and the conducting layer to form a plurality of word lines.

2. The method of claim 1, wherein patterning and etching the semiconductor layer comprises:

forming a cap layer over the semiconductor layer;

etching the cap layer and the semiconductor layer to form bitline regions comprising remaining portions of the cap layer and the semiconductor layer;

forming a dielectric layer over the etched cap and semiconductor layers;

etching a portion of the dielectric layer to form dielectric regions between the bitline regions and on top of the remaining portions of the cap layer; and

removing the remaining portions of the cap layer thereby removing the portions of the dielectric layer on top of the cap layer.

3. The method of claim 2, wherein the cap layer comprises a nitride layer.

4. The method of claim 2, wherein the dielectric layer comprises silicon dioxide.

5. The method of claim 4, wherein the silicon dioxide is deposited using high density plasma, chemical vapor deposition.

6. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

7. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming an oxide-nitride-oxide (ONO), nitride read only memory structure.

8. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a Band-gap Engineered (BE)-SONOS structure.

9. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a silicon-oxide-nitride-silicon (SONS) structure.

10. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a top BE-SON)OS structure.

11. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a top silicon-oxide-nitride-oxide-silicon-oxide-silicon (SONOSOS) structure.

12. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a bottom SOSONOS structure.

13. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a silicon-oxide-nitride-oxide-nitride-silicon (SONONS) structure.

14. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a silicon nitride (SiN) layer.

15. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a SiON layer.

16. The method of claim 1, wherein forming each of the first and second trapping structures comprises depositing a Hi-K material.

17. The method of claim 16 wherein the Hi-K material is HfO₂, AlN, or Al₂O₃.

18. The method of claim 1, further comprising forming source/drain regions in the regions of the plurality of bitlines not covered by the plurality of wordlines.

19. The method of claim 18, wherein the semiconductor layer comprises a P-type semiconductor material, and wherein forming the source drain regions comprises forming N+ regions in the P-type semiconductor material.

20. The method of claim 19, wherein the N+ regions are formed using As or P.

21. The method of claim 1, wherein the conducting layer comprises polysilicon material.

22. The method of claim 21, wherein the conducting layer comprises polysilicon/silicide/polysilicon material.

23. The method of claim 21, wherein the conducting layer comprises a metal.

24. The method of claim 23, wherein the metal is aluminum, copper, or tungsten.

25. The method of claim 1, further comprising forming a second bit line layer over the first wordline layer.

26. The method of claim 25, further comprising forming a second word line layer over the first bit line layer.

27. A method for fabricating a non-volatile memory device comprising a plurality of bitline layers and a plurality of word line layers sequentially formed on top of each other, the method comprising:

forming a first bitline layer;

forming a first word line layer over the first bitline layer, wherein forming the first word line layer comprises;

sequentially forming a trapping structure and a conducting layer;

patterning and etching the trapping structure and the conducting layer to form a plurality of word lines; and

forming a dielectric layer over the first word line layer.

28. The method of claim 27, further comprising forming a second bitline layer over the dielectric layer.

29. The method of claim 28, further comprising forming a second word line layer over the second bit line layer.

30. The method of claim 27, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

31. The method of claim 27, wherein forming the trapping structure comprises forming an oxide-nitride-oxide (ONO) structure.

32. The method of claim 27, wherein forming the trapping structure comprises forming a Band-gap Engineered (BE)-SONOS structure.

33. The method of claim 27, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-silicon (SONS) structure.

34. The method of claim 27, wherein forming the trapping structure comprises forming a top BE-SONOS structure.

35. The method of claim 27, wherein forming the trapping structure comprises forming a top silicon-oxide-nitride-oxide-silicon-oxide-silicon (SONOSOS) structure.

36. The method of claim 27, wherein forming the trapping structure comprises forming a bottom SOSONOS structure.

37. The method of claim 27, wherein forming the trapping structure comprises forming a silicon-oxide-nitride-oxide-nitride-silicon (SONONS) structure.

38. The method of claim 27, wherein forming the trapping structure comprises forming a silicon nitride (SiN) layer.

39. The method of claim 27, wherein forming the trapping structure comprises forming a SiON layer.

40. The method of claim 27, wherein forming the trapping layer comprises depositing a Hi-K material.

41. The method of claim 40, wherein the Hi-K material is HfO₂, AlN, or Al₂)₃.

42. The method of claim 27, further comprising forming source/drain regions in the regions of the plurality of bitlines not covered by the plurality of wordlines.

43. The method of claim 27, wherein the conducting layer comprises polysilicon material.

44. A stacked non-volatile memory device comprising:

a plurality of bit line layers, each of the plurality of bit liner layers comprising a plurality of bitlines formed from a semiconductor material and separated by dielectric regions; and

a plurality of wordline layers, each of the plurality of wordline layers comprising a plurality of wordlines each wordline including,

a first trapping structure.

a conducting layer, and

a second trapping structure.

45. The device of claim 44, wherein the semiconductor material comprises silicon, germanium, or silicon-germanium.

46. The device of claim 44, wherein the first trapping structure comprise a oxide-nitride-oxide (ONO) structure.

47. The method of claim 44, wherein the first trapping structure comprises a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

48. The method of claim 44, wherein the first trapping structure comprises a Band-gap Engineered (BE)-SONOS structure.

49. The method of claim 44, wherein the first trapping structure comprises a silicon-oxide-nitride-silicon (SONS) structure.

50. The method of claim 44, wherein the first trapping structure comprises a top BE-SONOS structure.

51. The method of claim 44, wherein the first trapping structure comprises a top silicon-oxide-nitride-oxide-silicon-oxide-silicon (SONOSOS) structure.

52. The method of claim 44, wherein the first trapping structure comprises a bottom SOSONOS structure.

53. The method of claim 44, wherein the first trapping structure comprises forming a silicon-oxide-nitride-oxide-nitride-silicon (SONONS) structure.

54. The device of claim 44, wherein the first trapping structure comprises a nitride layer.

55. The device of claim 54, wherein the nitride layer is a silicon nitride (SiN) layer.

56. The device of claim 54, wherein the nitride layer is a SiON layer.

57. The device of claim 44, wherein the first trapping structure comprises a Hi-K material.

58. The device of claim 57, wherein the Hi-K material is HfO₂, AlN, or Al₂O₃.

59. The device of claim 44, wherein the conducting layer comprises polysilicon.

60. The device of claim 44, wherein the conducting layer comprises polysilicon/silicide/polysilicon.

61. The device of claim 44, wherein the conducting layer comprises metal.

62. The device of claim 61, wherein the metal is Al, Cu, or W.