Thin Film Transistor Array Panel and Manufacturing Method Thereof
First Claim
1. A method of manufacturing a thin film transistor array panel, the method comprising:
- forming a gate line, a data line, and a thin film transistor on a substrate;
depositing first and second passivation layers in sequence;
patterning the second passivation layer using a photo mask having a light transmitting area, a light blocking area, and a slit area disposed partly surrounding the light transmitting area;
patterning the first passivation layer; and
forming a pixel electrode on the passivation layer.
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Accused Products
Abstract
A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.
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Citations
11 Claims
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1. A method of manufacturing a thin film transistor array panel, the method comprising:
- forming a gate line, a data line, and a thin film transistor on a substrate;
depositing first and second passivation layers in sequence;
patterning the second passivation layer using a photo mask having a light transmitting area, a light blocking area, and a slit area disposed partly surrounding the light transmitting area;
patterning the first passivation layer; and
forming a pixel electrode on the passivation layer. - View Dependent Claims (2, 3, 4)
- forming a gate line, a data line, and a thin film transistor on a substrate;
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5. A method of manufacturing a thin film transistor array panel, the method comprising:
- forming a gate line and a storage electrode on a substrate;
depositing a gate insulating layer on the gate line and the storage electrode;
depositing a semiconductor layer on the gate insulating layer;
patterning the semiconductor layer and the gate insulating layer using a photo mask including a alit area such that the gate insulating area includes a first portion disposed on the gate line and a second portion disposed on the storage electrode and having a thickness smaller than the first portion;
depositing first and second passivation layers in sequence;
patterning the second and the first passivation layers to form a contact hole exposing at least a portion of the drain electrode; and
forming a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the contact hole. - View Dependent Claims (6)
- forming a gate line and a storage electrode on a substrate;
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7. A method of manufacturing a thin film transistor array panel, the method comprising:
- forming a gate line and a storage electrode on a substrate;
forming a gate insulating layer on the gate line and the storage electrode;
forming a semiconductor layer on the gate insulating layer;
forming a data line and a drain electrode having an opening exposing a portion of the gate insulating layer;
depositing first and second passivation layers in sequence;
patterning the second and the first passivation layers to form a first contact hole exposing at least the opening of the drain electrode;
reducing a thickness of the exposed portion of the gate insulating layer through the opening; and
forming a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the contact hole. - View Dependent Claims (8, 9, 10, 11)
- forming a gate line and a storage electrode on a substrate;
Specification