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MULTI-LEVEL MEMORY CELL ARRAY WITH LATERAL FLOATING SPACERS

  • US 20070134875A1
  • Filed: 11/07/2006
  • Published: 06/14/2007
  • Est. Priority Date: 12/20/2002
  • Status: Abandoned Application
First Claim
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1. A method of making a non-volatile MOS memory transistor capable of storing two binary bits comprising:

  • defining a poly gate having opposed sidewalls and separated from a semiconductor substrate by gate oxide;

    defining first and second conductive poly spacers adjacent opposite sidewalls of the poly gate and separated therefrom and from the substrate by tunnel oxide;

    defining subsurface doped source and drain electrodes in the substrate after formation of the poly gate, the source and drain each adjacent to one of the first and second poly spacers; and

    defining a conductive region over the poly gate for applying control signals in combination with the source and drain regions thereby forming a multi-bit memory transistor capable of storing a binary bit in each of the poly spacers.

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