MULTI-LEVEL MEMORY CELL ARRAY WITH LATERAL FLOATING SPACERS

• US 20070134875A1
• Filed: 11/07/2006
• Published: 06/14/2007
• Est. Priority Date: 12/20/2002
• Status: Abandoned Application

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lojek, Bohumil
• Application Number:
  US11/557,179
• Publication Number:
  US 20070134875A1
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An array of multi-level non-volatile memory transistors features a transistor construction with a conductive polysilicon control gate having opposed sidewalls insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. The array has auxiliary low voltage transistors which may be made at the same time as the formation of the memory transistors. The auxiliary transistors apply opposite phase clock pulses to source and drain electrodes of transistors in the array so that first one side of each memory transistor may be written to, or read, then the other side.

Claims

1. A method of making a non-volatile MOS memory transistor capable of storing two binary bits comprising:

defining a poly gate having opposed sidewalls and separated from a semiconductor substrate by gate oxide;

defining first and second conductive poly spacers adjacent opposite sidewalls of the poly gate and separated therefrom and from the substrate by tunnel oxide;

defining subsurface doped source and drain electrodes in the substrate after formation of the poly gate, the source and drain each adjacent to one of the first and second poly spacers; and

defining a conductive region over the poly gate for applying control signals in combination with the source and drain regions thereby forming a multi-bit memory transistor capable of storing a binary bit in each of the poly spacers.

2. The method of claim 1 further defined by forming gates of low voltage p and n MOS transistors at the same time as defining the poly gate of the memory transistor.