Hafnium tantalum titanium oxide films

• US 20070134942A1
• Filed: 12/08/2005
• Published: 06/14/2007
• Est. Priority Date: 12/08/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Ahn, Kie
• Granted Patent: US 7,592,251 B2
• Time in Patent Office: Days
• US Class Current: 438/785
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31637 Deposition of Tantalum oxides, e.g. Ta2O5
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using atomic layer deposition.

Claims

1. A method comprising forming a layer of hafnium tantalum titanium oxide using atomic layer deposition.

2. The method of claim 1, wherein the method includes:

forming a layer of hafnium oxide by atomic layer deposition;

forming a layer of tantalum oxide by atomic layer deposition;

forming a layer of titanium oxide by atomic layer deposition; and

annealing the layers of hafnium oxide, tantalum oxide, and titanium oxide to form the layer of hafnium tantalum titanium oxide.

3. The method of claim 2, wherein annealing the layers of hafnium oxide, tantalum oxide, and titanium oxide includes annealing by rapid thermal annealing to form the layer of hafnium tantalum titanium oxide.

4. The method of claim 2, wherein forming the layers of hafnium oxide, tantalum oxide, and titanium oxide includes performing the formation of the layers of hafnium oxide, tantalum oxide, and titanium oxide in a predetermined order.

5. The method of claim 2, wherein the method includes forming the layers of hafnium oxide, tantalum oxide, and titanium oxide in a dielectric stack before annealing.

6. The method of claim 5, wherein forming the layers of hafnium oxide, tantalum oxide, and titanium oxide in a dielectric stack includes forming alternating layers of TiO_z, TaO_y, and HfO_x.

7. The method of claim 1, wherein forming a dielectric layer containing a hafnium tantalum titanium oxide film includes forming an amorphous HfTaTiO_x layer.

8. The method of claim 1, wherein using atomic layer deposition includes using a titanium halide precursor.

9. The method of claim 8, wherein using a titanium halide precursor includes using a titanium chloride precursor.

10. The method of claim 1, wherein using atomic layer deposition includes using a titanium nitride precursor.

11. The method of claim 1, wherein using atomic layer deposition includes using a titanium isopropoxide precursor.

12. The method of claim 1, wherein using atomic layer deposition includes using a hafnium nitride precursor.

13. The method of claim 1, wherein using atomic layer deposition includes using a hafnium halide precursor.

14. The method of claim 13, wherein using a hafnium halide precursor includes using a haffnium iodine precursor.

15. The method of claim 1, wherein using atomic layer deposition includes using a Ta(OC₂H₅)₅ precursor.

16. The method of claim 1, wherein using atomic layer deposition includes using a tantalum halide precursor.

17. The method of claim 1, wherein forming the layer of hafnium tantalum titanium oxide includes forming the layer of hafnium tantalum titanium oxide as a dielectric in a capacitor in an integrated circuit.

18. The method of claim 1, wherein forming the layer of hafnium tantalum titanium oxide includes forming the layer of hafnium tantalum titanium oxide as a dielectric in a capacitor of a dynamic random access memory.

19. The method of claim 1, wherein forming the layer of hafnium tantalum titanium oxide includes forming the layer of hafnium tantalum titanium oxide as a gate insulator in a silicon complementary metal oxide semiconductor transistor.

20. The method of claim 1, wherein forming the layer of hafnium tantalum titanium oxide includes forming the layer of hafnium tantalum titanium oxide as a tunnel gate insulator in a flash memory device.

21. The method of claim 1, wherein forming the layer of hafnium tantalum titanium oxide includes forming the layer of hafnium tantalum titanium oxide as an inter-gate insulator in a flash memory device.

22. The method of claim 1, wherein forming the layer of hafnium tantalum titanium oxide includes forming the layer of hafnium tantalum titanium oxide as a dielectric region in a NROM flash memory.

23. The method of claim 22, wherein forming the layer of hafnium tantalum titanium oxide as a dielectric region in a NROM flash memory includes forming the layer of hafnium tantalum titanium oxide in a nanolaminate.

24. The method of claim 1, wherein forming the layer of hafnium tantalum titanium oxide includes forming the layer of hafnium tantalum titanium oxide as a dielectric region in a memory and providing contacts to couple the memory to a controller in an electronic system.

25. A method comprising:

forming a first conductive layer;

forming a dielectric layer on the first conductive layer, the dielectric layer containing a hafnium tantalum titanium oxide film, including forming the hafnium tantalum titanium oxide film by;

forming a layer of HfO₂ by atomic layer deposition;

forming a layer of TaO₂ by atomic layer deposition;

forming a layer of TiO₂ by atomic layer deposition; and

annealing the layers of HfO₂, TaO₂, and TiO₂ to form the hafnium tantalum titanium oxide film; and

forming a second conductive layer on the dielectric layer to form a capacitor.

26. The method of claim 25, wherein annealing the layers of HfO₂, TaO₂, and TiO₂ includes annealing by rapid thermal annealing to form the hafnium tantalum titanium oxide film.

27. The method of claim 25, wherein the method includes forming the layers of HfO₂, TaO₂, and TiO₂ in a dielectric stack before annealing.

28. The method of claim 25, wherein forming the layers of HfO₂, TaO₂, and TiO₂ in a dielectric stack includes forming alternating layers of HfO₂, TaO₂, and TiO₂.

29. The method of claim 25, wherein forming the layers of HfO₂, TaO₂, and TiO₂ includes performing the formation of the layers of HfO₂, TaO₂, and TiO₂ in a predetermined order.

30. The method of claim 25, wherein the method includes forming the first conductive layer, the dielectric layer, and the second conductive layer as a capacitor in an analog integrated circuit.

31. The method of claim 25, wherein the method includes forming the first conductive layer, the dielectric layer, and the second conductive layer as a capacitor in a radio frequency integrated circuit.

32. The method of claim 25, wherein the method includes forming the first conductive layer, the dielectric layer, and the second conductive layer as a capacitor in a mixed signal integrated circuit.

33. A method comprising:

forming a memory array including forming a dielectric layer in a cell of the memory array, wherein forming the dielectric layer includes forming a hafnium tantalum titanium oxide film by;

forming a layer of hafnium oxide by atomic layer deposition;

forming a layer of tantalum oxide by atomic layer deposition;

forming a layer of titanium oxide by atomic layer deposition; and

annealing the layers of hafnium oxide, tantalum oxide, and titanium oxide to form the hafnium tantalum titanium oxide film.

34. The method of claim 33, wherein annealing the layers of hafnium oxide, tantalum oxide, and titanium oxide includes annealing by rapid thermal annealing to form the hafnium tantalum titanium oxide film.

35. The method of claim 33, wherein forming the layers of hafnium oxide, tantalum oxide, and titanium oxide includes performing the formation of the layers of hafnium oxide, tantalum oxide, and titanium oxide in a predetermined order.

36. The method of claim 33, wherein the method includes forming the layers of hafnium oxide, tantalum oxide, and titanium oxide in a dielectric stack before annealing.

37. The method of claim 33, wherein forming the layers of hafnium oxide, tantalum oxide, and titanium oxide includes forming alternating layers of TiO_x, TaO_x, and HfO_x.

38. The method of claim 33, wherein forming a dielectric layer includes forming the dielectric layer substantially of the hafnium tantalum titanium oxide film.

39. The method of claim 33, wherein forming a memory array includes forming a memory array of a dynamic random access memory.

40. The method of claim 33, wherein forming the dielectric layer includes forming the dielectric layer as a dielectric in a capacitor of a dynamic random access memory.

41. The method of claim 33, wherein forming the dielectric layer includes forming the dielectric layer as a tunnel gate insulator in a flash memory device.

42. The method of claim 33, wherein forming the dielectric layer includes forming the dielectric layer as an inter-gate insulator in a flash memory device.

43. The method of claim 33, wherein forming the dielectric layer includes forming the dielectric layer as a dielectric region to store charge in a NROM flash memory.

44. A method comprising:

providing a controller;

coupling an integrated circuit to the controller, the integrated circuit having a dielectric layer containing a hafnium tantalum titanium oxide film, the hafnium tantalum titanium oxide film formed by;

forming a layer of hafnium oxide by atomic layer deposition;

forming a layer of tantalum oxide by atomic layer deposition;

forming a layer of titanium oxide by atomic layer deposition; and

annealing the layers of hafnium oxide, tantalum oxide, and titanium oxide to form the hafnium tantalum titanium oxide film.

45. The method of claim 44, wherein annealing the layers of hafnium oxide, tantalum oxide, and titanium oxide includes annealing by rapid thermal annealing to form the hafnium tantalum titanium oxide film.

46. The method of claim 44, wherein forming the layers of hafnium oxide, tantalum oxide, and titanium oxide includes performing the formation of the layers of hafnium oxide, tantalum oxide, and titanium oxide in a predetermined order.

47. The method of claim 44, wherein forming the layers of hafnium oxide, tantalum oxide, and titanium oxide includes forming alternating layers of TiO_x, TaO_x, and HfO_x before annealing.

48. The method of claim 44, wherein forming a dielectric layer includes forming the dielectric layer substantially of the hafnium tantalum titanium oxide film.

49. The method of claim 44, wherein coupling an integrated circuit to the controller includes coupling a memory device formed as the integrated circuit, the memory device having the dielectric layer containing the hafnium tantalum titanium oxide film.

50. The method of claim 44, wherein providing a controller includes providing a processor.

51. The method of claim 44, wherein coupling an integrated circuit to the controller includes coupling a mixed signal integrated circuit formed as the integrated circuit having the dielectric layer containing the hafnium tantalum titanium oxide film.

52. The method of claim 44, wherein the method includes forming an information handling system.

53. The method of claim 52, wherein forming an information handling system includes forming a wireless system.

54. An electronic device comprising:

a dielectric layer in an integrated circuit on a substrate, the dielectric layer including a hafnium tantalum titanium oxide layer structured as one or more mono layers.

55. The electronic device of claim 54, wherein the dielectric layer is substantially the hafnium tantalum titanium oxide layer.

56. The electronic device of claim 54, wherein the electronic device includes a capacitor having the dielectric layer as a capacitor dielectric.

57. The electronic device of claim 54, wherein the electronic device includes a transistor in which the dielectric layer is disposed.

58. The electronic device of claim 54, wherein the electronic device includes a memory in which the dielectric layer is disposed.

59. The electronic device of claim 54, wherein the electronic device includes connections to couple a signal from other components in an electronic system to a conductive layer contacting the dielectric layer.