Scheme for securing locally generated data with authenticated write operations

• US 20070136407A1
• Filed: 12/08/2005
• Published: 06/14/2007
• Est. Priority Date: 12/08/2005
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rudelic, John
• Granted Patent: US 8,219,829 B2
• Time in Patent Office: Days
• US Class Current: 708/250
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00

Abstract

A scheme for securing a locally generated data on a system using authenticated write operations is disclosed. According to an embodiment of the present invention, a private/public key pair is randomized and repeatedly generated to protect operations to data blocks.

Claims

1. A method comprising:

generating a private key and a corresponding public key;

storing the corresponding public key in a memory device; and

securing a write operation to the memory device with the private key.

2. The method as recited in claim 1, wherein the memory device uses the corresponding public key to verify the write operation.

3. The method as recited in claim 1, wherein securing the write operation comprises signing the write operation.

4. The method as recited in claim 1, wherein the private key and the corresponding public key comprise a random, non-predictable key pair.

5. The method as recited in claim 1, further comprising:

generating another private key and another corresponding public key;

replacing the public key with the other corresponding public key in the memory device; and

securing another write operation with the other private key.

6. The method as recited in claim 5, wherein the generating the private key and the generating the other private key occur at a predefined time interval.

7. The method as recited in claim 5, wherein the generating the private key and the generating the other private key occur at a random time interval.

8. The method as recited in claim 1, wherein the private key and the corresponding public key protect writes to a first block of memory in a flash device and another private key and another corresponding public key protect writes to a second block of memory in the memory device.

9. The method as recited in claim 1, wherein the write operation comprises an update to flash file system data.

10. The method as recited in claim 1, wherein the write operation comprises a write to a block of memory.

11. A system comprising:

a processor to generate a private key and a corresponding public key;

a memory device to store the corresponding public key; and

an input port from coupled to the processor and the memory device;

wherein the processor further to secure a write operation to the memory device with the private key.

12. The system as recited in claim 11, wherein the memory device comprises a controller to use the corresponding public key to verify the write operation.

13. The system as recited in claim 11, wherein the processor signs the write operation to secure the write operation using the private key.

14. The system as recited in claim 11, wherein the private key and the corresponding public key comprise a random, non-predictable key pair.

15. The system as recited in claim 11, wherein the processor is further to generate another private key and another corresponding public key, replace the public key with the other corresponding public key in the memory device, and secure another write operation with the other private key.

16. The system as recited in claim 15, wherein the processor generates the private key and the other private key at a predefined time interval.

17. The system as recited in claim 15, wherein the processor generates the private key and the other private key at a random time interval.

18. The system as recited in claim 11, wherein the private key and the corresponding public key protect writes to a first block of memory in a flash device and another private key and another corresponding public key protect writes to a second block of memory in the memory device.

19. A memory device comprising:

a memory array; and

a controller configured to authenticate a write operation to the memory array using a public key stored on the memory device.

20. The memory device as recited in claim 19, further comprising:

a public key storage to store the public key;

and a key register to associate the public key with a particular block of the memory array, the public key used to authenticate operations to the particular block of the memory array.

21. The memory device as recited in claim 19, wherein the public key storage is capable of storing multiple public keys, each of the multiple keys used to authenticate operations to different block of the memory array.