TCP/IP offload network interface device

• US 20070136495A1
• Filed: 02/02/2007
• Published: 06/14/2007
• Est. Priority Date: 10/14/1997
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Boucher, Laurence, Craft, Peter, Starr, Daryl, Blightman, Stephen, Higgen, David, Philbrick, Clive
• Granted Patent: US 7,853,723 B2
• Time in Patent Office: Days
• US Class Current: 709/250
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The TONID also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the TONID to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the TONID as a communication control block (CCB) that can be passed back to the host for message processing by the host. The TONID contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

Claims

1. A method, comprising:

maintaining a set of communication control blocks (CCBs), some of the set of CCBs being maintained in a static random access memory (SRAM), others of the set of CCBs being maintained in a dynamic random access memory (DRAM), wherein a first plurality of the set of CCBs is under control of a network interface device, and wherein a second plurality of the set of CCBs is under control of a processing device, the processing device being coupled to the network interface device, the processing device executing a network protocol stack;

receiving a TCP/IP packet onto the network interface device from a network, the TCP/IP packet including a data portion and a header portion;

using a content addressable memory (CAM) on the network interface device to determine that the TCP/IP packet is associated with one of the first plurality of CCBs;

determining on the network interface device that said one CCB is stored in the DRAM and transferring said one CCB into the SRAM; and

transferring the data portion of the TCP/IP packet from the network interface device and into a destination without transferring the header portion of the TCP/IP packet into the destination, the destination having been determined by the processing device, wherein the network protocol stack executing on the processing device performs substantially no TCP protocol processing on the TCP/IP packet.

2. The method of claim 1, further comprising:

receiving a second TCP/IP packet onto the network interface device from the network;

determining that the second TCP/IP packet is not associated with any one of the first plurality of CCBs; and

transferring the second TCP/IP packet from the network interface device and to the processing device, the processing device thereafter performing TCP protocol processing on the second TCP/IP packet.

3. The method of claim 1, wherein the TCP/IP packet has a TCP destination port, a TCP source port, an IP destination address, and an IP source address, the method further comprising:

generating a context hash from the TCP source and destination ports and from the IP source and destination addresses, the network interface device using the context hash to identify said one CCB associated with the TCP/IP packet.

4. The method of claim 1, wherein control of a CCB can be passed from the network interface device to the processing device.

5. The method of claim 1, wherein control of a CCB can be passed from the processing device to the network interface device.

6. The method of claim 1, wherein the network interface device comprises specialized hardware for generating a hash from the header portion of the TCP/IP packet, and wherein the network interface device further comprises a processor, the processor accessing the hash and using the hash to determine that the TCP/IP packet is associated with said one of the first plurality of CCBs.

7. The method of claim 6, wherein the specialized hardware comprises a sequencer.

8. The method of claim 1, wherein the network interface device comprises specialized hardware for generating a summary, and wherein the network interface device further comprises a processor, the processor accessing the summary and using the summary to determine that the TCP/IP packet is associated with said one of the first plurality of CCBs.

9. The method of claim 8, wherein the summary includes a hash.

10. The method of claim 8, wherein the summary includes information indicative of whether the TCP/IP packet employs both the TCP protocol and the IP protocol.

11. The method of claim 1, wherein the processing device is a central processing unit (CPU), and wherein the network interface device is integrated with the CPU.

12. The method of claim 1, wherein the processing device is a host, and wherein the network interface device is integrated into the host.

13. The method of claim 1, wherein the processing device is a central processing unit (CPU), the network interface device being integrated with the CPU, and wherein the network interface device comprises a plurality of processors, the plurality of processors sharing the first plurality of CCBs.

14. A network interface device that is coupled to a processing device, the processing device executing a protocol stack, the network interface device comprising:

an amount of SRAM, the SRAM storing a first plurality of communication control blocks (CCBs) that are under control of the network interface device;

an amount of DRAM, the DRAM storing a second plurality of CCBs that are under control of the network interface device;

specialized hardware that analyzes a TCP/IP packet received onto the network interface device from a network, the TCP/IP packet comprising a data portion and a header portion, the specialized hardware generating a summary from the TCP/IP packet;

a processor that uses the summary and a content addressable memory to determine whether the TCP/IP packet can be processed via a fast-path by the network interface device as opposed to being processed via a slow-path using the protocol stack, wherein the processor determines that the TCP/IP packet can be processed via the fast-path, the TCP/IP packet being associated with one of the second plurality of CCBs, the processor causing said one of the second plurality of CCBs to be moved from the DRAM into the SRAM; and

a mechanism that moves the data portion of the TCP/IP packet from the network interface device and into a destination identified by the processing device, the data portion of the TCP/IP packet being written into the destination without the header portion of the TCP/IP packet being written into the destination and without the protocol stack doing substantial TCP protocol processing on the TCP/IP packet.

15. The network interface device of claim 14, wherein the specialized hardware generates from the TCP/IP packet a hash, the hash being a part of the summary, the summary being used by the processor to make the determination that the packet can be processed via the fast-path.

16. The network interface device of claim 14, wherein the summary includes information indicative of whether the TCP/IP packet conforms to both the TCP protocol and the IP protocol.

17. A network interface device that is integrated with a processing device, the processing device executing a protocol stack, the network interface device comprising:

an amount of SRAM, the SRAM storing a first plurality of communication control blocks (CCBs) that are under control of the network interface device;

an amount of DRAM, the DRAM storing a second plurality of CCBs that are under control of the network interface device;

means for analyzing a packet received onto the network interface device from a network and for generating from the packet a summary, the packet comprising a data portion and a header portion, the header portion including a TCP destination port value and a TCP source port value;

a processor that uses the summary and a content addressable memory to determine whether the packet can be processed via a fast-path by the network interface device as opposed to being processed via a slow-path using the protocol stack, wherein the packet is associated with one of the second plurality of CCBs, the processor causing said one of the second plurality of CCBs to be moved from the DRAM into the SRAM; and

a mechanism that moves the data portion of the packet from the network interface device and into a destination accessible by the processing device, the data portion of the packet being written into the destination without the header portion of the packet being written into the destination and without the protocol stack doing substantial TCP protocol processing on the packet.

18. The network interface device of claim 17, further comprising a second processor, wherein the processor and the second processor share use of the first plurality of CCBs.

19. The network interface device of claim 17, wherein there is a third plurality of CCBs that are under control of the processing device, wherein control of a CCB can be passed from the processing device to the network interface device.

20. The network interface device of claim 17, wherein the means is also for performing header checksum validation on the packet.