Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method

• US 20070136647A1
• Filed: 09/13/2006
• Published: 06/14/2007
• Est. Priority Date: 11/30/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanai, Tatsunori, Yoshii, Kenichiro
• Granted Patent: US 7,761,779 B2
• Time in Patent Office: Days
• US Class Current: 714/785
• CPC Class Codes: G06F 11/1032 Simple parity

Abstract

An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.

Claims

1. An access control apparatus to control an access among a writer, a reader, and a memory, comprising:

a parity generator that generates a parity for original data to be written into the memory;

a parity adder that generates parity-added data by adding the parity generated by the parity generator to the original data;

a first syndrome generator that generates a first syndrome which is a value associated with a first access code used by the writer to request writing of the original data into the memory;

a first mask generator that generates the first mask data, based on the first syndrome, the first access code, and a first memory address at which the original data is to be written by the writer;

a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data;

a writing unit that writes the first post-operation data into the memory;

a second syndrome generator that generates a second syndrome which is a value associated with a second access code used by the reader to request reading of data from the memory;

a second mask generator that generates the second mask data, based on the second syndrome, the second access code, and a second memory address from which the data is to be read by the reader;

a reading unit that reads the first post-operation data from the memory;

a second XOR unit that obtains second post-operation data by calculating an XOR between the second mask data and the first post-operation data;

a data syndrome calculator that calculates a real data syndrome based on the second post-operation data; and

an output determining unit that determines whether the second post-operation data is to be output as the original data, based on the real data syndrome.

2. The access control apparatus according to claim 1, further comprising:

a first code acquirer that acquires the first access code from the writer; and

a second code acquirer that acquires the second access code from the reader, wherein

the first syndrome generator generates the first syndrome, based on the first access code acquired by the first code acquirer, and

the second syndrome generator generates the second syndrome, based on the second access code acquired by the second code acquirer.

3. The access control apparatus according to claim 2, wherein

the first code acquirer acquires the first access code via a first dedicated line that is connected to the writer;

and

the second code acquirer acquires the second access code via a second dedicated line that is connected to the reader.

4. The access control apparatus according to claim 1, further comprising:

a writer ID acquirer that acquires a writer ID for identifying the writer;

a first code specifier that determines the first access code, based on the writer ID acquired by the writer ID acquirer;

a reader ID acquirer that acquires a reader ID for identifying the reader; and

a second code specifier that determines the second access code, based on the reader ID acquired by the reader ID acquirer, wherein

the first syndrome generator generates the first syndrome, based on the first access code determined by the first code specifier, and

the second syndrome generator generates the second syndrome, based on the second access code determined by the second code specifier.

5. The access control apparatus according to claim 4, further comprising:

a first code storage that stores the writer ID and the first access code associated with each other; and

a second code storage that stores the reader ID and the second access code associated with each other, wherein

the first code specifier determines the first access code that is stored in the first code storage and is associated with the writer ID acquired by the writer ID acquirer, and

the second code specifier determines the second access code that is stored in the second code storage and is associated with the reader ID acquired by the reader ID acquirer.

6. The access control apparatus according to claim 5, further comprising:

a first address acquirer that acquires the first memory address from the writer; and

a second address acquirer that acquires the second memory address from the reader, wherein

the first code storage further stores the first memory address associated with the first access code,

the first code specifier determines the first access code that is stored in the first code storage and is associated with the first memory address acquired by the first address acquirer,

the second code storage further stores the second memory address associated with the second access code, and

the second code specifier determines the second access code that is stored in the second code storage and is associated with the second memory address acquired by the second address acquirer.

7. The access control apparatus according to claim 1, further comprising:

a first address acquirer that acquires the first memory address from the writer;

a first code storage that stores the first memory address and the first access code associated with each other;

a first code specifier that determines the first access code that is stored in the first code storage and is associated with the first memory address acquired by the first address acquirer;

a second address acquirer that acquires the second memory address from the reader;

a second code storage that stores the second memory address and the second access code associated with each other; and

a second code specifier that determines the second access code that is stored in the second code storage and is associated with the second memory address acquired by the second address acquirer, wherein

the first syndrome generator generates the first syndrome, based on the first access code determined by the first code specifier, and

the second syndrome generator generates the second syndrome, based on the second access code determined by the second code specifier.

8. The access control apparatus according to claim 1, wherein

the first mask generator comprises

a first data mask generator that generates a data mask for masking the original data, based on the first access code and the first memory address;

and

a first parity mask generator that generates a parity mask for masking the parity generated by the parity generator, the parity mask being an XOR between a syndrome of the data mask generated by the data mask generator and the first syndrome generated by the first syndrome generator,

the second mask generator comprises

a second data mask generator that generates a data mask for masking a portion of the first post-operation data corresponding to the original data, based on the second access code and the second memory address; and

a second parity mask generator that generates a parity mask for masking a portion of the first post-operation data corresponding to the parity, the parity mask being an XOR between a syndrome of the data mask generated by the data mask generator and the second syndrome generated by the second syndrome generator,

the first XOR unit calculates an XOR between the original data and the data mask generated by the first data mask generator, and calculates an XOR between the parity and the parity mask generated by the first parity mask generator, and

the second XOR unit calculates an XOR between a data portion of the first post-operation data and the data mask generated by the second data mask generator, and an XOR between a parity portion of the first post-operation data and the parity mask generated by the second parity mask generator.

9. The access control apparatus according to claim 8, wherein the first data mask generator and the second data mask generator each comprise a Linear Feedback Shift Registers (LFSR) delay calculator.

10. The access control apparatus according to claim 9, wherein the LFSR delay calculator operates using a different parameter for each of the first access code and the second access code.

11. The access control apparatus according to claim 8, wherein the first data mask generator and the second data mask generator each comprise

a plurality of LFSR delay calculators;

and

an XOR unit that calculates an XOR between output values from at least two LFSR delay calculators among output values of the plurality of LFSR delay calculators.

12. The access control apparatus according to claim 11, wherein the LFSR delay calculator operates using a different parameter for each of the first access code and the second access code.

13. The access control apparatus according to claim 12, further comprising

a data mask generation information storage that stores parameters of the LFSR delay calculator, the parameters being associated with the first access code or the second access code, wherein

the LFSR delay calculator operates using the parameters that are stored in the data mask generation information storage and are associated with the first access code or the second access code.

14. The access control apparatus according to claim 8, wherein the first data mask generator and the second data mask generator each comprise a zero-shifter that shifts each memory address.

15. The access control apparatus according to claim 8, wherein the first data mask generator and the second data mask generator each comprise an address separator that changes values of successive memory addresses to values that are more distant to each other.

16. The access control apparatus according to claim 1, further comprising:

a writer address changer that changes the first memory address to a different address; and

a reader address changer that changes the second memory address to a different address, wherein

the first syndrome generator generates the first syndrome, based on the first memory address changed by the writer address changer,

the first mask generator generates the first mask data, based on the first memory address changed by the writer address changer,

the second syndrome generator generates the second syndrome, based on the second memory address changed by the reader address changer, and

the second mask generator generates the second mask data, based on the second memory address changed by the reader address changer.

17. The access control apparatus according to claim 1, wherein the writer and the reader are a processor or a process.

18. The access control apparatus according to claim 1, further comprising:

a random number generator that generates the same random numbers as random numbers generated in the memory;

an random XOR unit that performs an XOR operation between the random values generated by the random generator and a memory address of a region to be accessed in the memory; and

a post-operation address transmitter that transmits a post-operation address that is an operation result of the random XOR unit.

19. An access control system comprising:

a processor;

a memory controller; and

a memory access control apparatus that controls access to a memory,

the memory access control apparatus comprising

a parity generator that generates a parity for original data to be written into the memory;

a parity adder that generates parity-added data by adding the parity generated by the parity generator to the original data;

a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data, the first syndrome being a value associated beforehand with a first access code that is information to be used when a writer accesses the memory, the writer requesting writing of the original data into the memory;

a first mask generator that generates the first mask data, based on the first syndrome, the first access code, and a first memory address at which the original data is to be written;

a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data;

a writing unit that writes the first post-operation data into the memory;

a second syndrome generator that generates a second syndrome of second mask data to mask the first post-operation data, the second syndrome being a value associated beforehand with a second access code that is information to be used when a reader accesses the memory, the reader requesting reading of data from the memory;

a second mask generator that generates the second mask data, based on the second syndrome, the second access code, and a second memory address from which the data is to be read;

a reading unit that reads the first post-operation data from the memory;

a second XOR unit that obtains second post-operation data by calculating an XOR between the second mask data and the first post-operation data;

a data syndrome calculator that calculates a real data syndrome based on the second post-operation data; and

an output determining unit that determines whether the second post-operation data is to be output as the original data, based on the real data syndrome.

20. An access control system comprising:

a processor; and

a memory access control apparatus that controls access to a memory,

the memory access control apparatus comprising

a parity generator that generates a parity for original data to be written into the memory;

a parity adder that generates parity-added data by adding the parity generated by the parity generator to the original data;

a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data, the first syndrome being a value associated beforehand with a first access code that is information to be used when a writer accesses the memory, the writer requesting writing of the original data into the memory;

a first mask generator that generates the first mask data, based on the first syndrome, the first access code, and a first memory address at which the original data is to be written;

a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data;

a writing unit that writes the first post-operation data into the memory;

a second syndrome generator that generates a second syndrome of second mask data to mask the first post-operation data, the second syndrome being a value associated beforehand with a second access code that is information to be used when a reader accesses the memory, the reader requesting reading of data from the memory;

a second mask generator that generates the second mask data, based on the second syndrome, the second access code, and a second memory address from which the data is to be read;

a reading unit that reads the first post-operation data from the memory;

a second XOR unit that obtains second post-operation data by calculating an XOR between the second mask data and the first post-operation data;

a data syndrome calculator that calculates a real data syndrome based on the second post-operation data; and

an output determining unit that determines whether the second post-operation data is to be output as the original data, based on the real data syndrome.

21. A processor that is equipped with a memory controller and a memory access control apparatus that controls access to a memory,

the processor comprising:

a parity generator that generates a parity for original data to be written into the memory;

a parity adder that generates parity-added data by adding the parity generated by the parity generator to the original data;

a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data, the first syndrome being a value associated beforehand with a first access code that is information to be used when a writer accesses the memory, the writer requesting writing of the original data into the memory;

a first mask generator that generates the first mask data, based on the first syndrome, the first access code, and a first memory address at which the original data is to be written;

a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data;

a writing unit that writes the first post-operation data into the memory;

a second syndrome generator that generates a second syndrome of second mask data to mask the first post-operation data, the second syndrome being a value associated beforehand with a second access code that is information to be used when a reader accesses the memory, the reader requesting reading of data from the memory;

a second mask generator that generates the second mask data, based on the second syndrome, the second access code, and a second memory address from which the data is to be read;

a reading unit that reads the first post-operation data from the memory;

a second XOR unit that obtains second post-operation data by calculating an XOR between the second mask data and the first post-operation data;

a data syndrome calculator that calculates a real data syndrome based on the second post-operation data; and

an output determining unit that determines whether the second post-operation data is to be output as the original data, based on the real data syndrome.

22. An access control method comprising:

generating a parity for original data to be written into a memory;

generating parity-added data by adding the parity generated to the original data;

generating a first syndrome of first mask data to mask the parity-added data, the first syndrome being a value associated beforehand with a first access code that is information to be used when a writer accesses the memory, the writer requesting writing of the original data into the memory;

generating the first mask data based on the first syndrome, the first access code, and a first memory address at which the original data is to be written;

acquiring first post-operation data by calculating an XOR between the parity-added data and the first mask data;

writing the first post-operation data into the memory;

generating a second syndrome of second mask data to mask the first post-operation data, the second syndrome being a value associated beforehand with a second access code that is information to be used when a reader accesses the memory, the reader requesting reading of data from the memory;

generator that generates the second mask data, based on the second syndrome, the second access code, and a second memory address from which the data is to be read;

reading the first post-operation data from the memory;

obtaining second post-operation data by calculating an XOR between the second mask data and the first post-operation data;

calculating a real data syndrome based on the second post-operation data; and

determining whether the second post-operation data is to be output as the original data, based on the real data syndrome.

23. A memory access control apparatus, comprising:

a read request acquirer that acquires data to be read from a memory, and a memory address at which the data is to be read, the data and the memory address being acquired from a reader that requests the reading of the data from the memory;

a cache memory monitor that determines whether the memory address acquired by the read request acquirer is stored in a cache memory that stores data, a memory address of the data, and a requester access code in association with one another, the data being requested to be written into the memory by a writer that requests writing of the data into the memory or being requested to be read from the memory by the reader, the requester access code being information to be used when a writer or a reader that is allowed to access the data accesses the memory;

an access code comparator that compares the requester access code, which is associated with the memory address in the cache memory, with a second access code that is information to be used by the reader to access the memory, when the cache memory monitor determines that the memory address is stored in the cache memory; and

an output unit that outputs the data associated with the memory address in the cache memory to the reader, when the requestor access code matches the second access code.

24. The memory access control apparatus according to claim 23, wherein

the data stored in the memory is first post-operation data that is obtained by performing a predetermined operation on the data acquired by the read request acquirer, and

the memory access control apparatus further comprises

a second syndrome generator that generates a second syndrome of second mask data to mask the data stored in the memory, when the cache memory monitor determines that the memory address of the data acquired by the read request acquirer is not stored in the cache memory, the second syndrome being a value associated beforehand with the second access code;

a second mask generator that generates the second mask data, based on the second syndrome, the second access code, and the memory address;

a reading unit that reads the first post-operation data from the memory;

a first XOR unit that obtains second post-operation data by calculating an XOR between the second mask data and the first post-operation data read from the reading unit;

a data syndrome calculator that calculates a real data syndrome based on the post-operation data; and

an output determining unit that determines whether the second post-operation data is to be output as the data requested by the reader, based on the data syndrome.

25. The memory access control apparatus according to claim 23, further comprising:

a write request acquirer that acquires data to be written into the memory, and a memory address at which the data is to be written, the data and the memory address being acquired from a writer that requests the writing of the data into memory;

an code storage that stores the memory address in association with a first access code that is information to be used when a writer allowed to write data at the memory address makes an access at the memory address; and

a data storage that stores the data and the memory address acquired by the write request acquirer in association with the first access code that is the information to be used by the writer accessing the memory in the cache memory, when the memory address acquired by the write request acquirer is associated with the first access code of the writer in the access code storage.

26. The memory access control apparatus according to claim 24, further comprising:

a parity generator that generates a parity of the data stored in the data storage;

a parity adder that generates parity-added data by adding the parity generated by the parity generator to the data;

a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data having the parity-added thereto, the first syndrome being a value that is associated beforehand with the first access code that is the information used by the writer to write the data into the memory;

a first mask generator that generates the first mask data, based on the first syndrome, the first access code, and the memory address;

a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and

a writing unit that writes the first post-operation data as the data into the memory.

27. An access control system comprising:

a processor;

a cache memory; and

a memory access control apparatus that controls access to a memory,

the cache memory storing data requested by a writer that request writing of the data into the memory or a reader that requests reading of the data from the memory, a memory address of the data, and a requester access code that is information to be used when a writer or a reader that is allowed to access the data accesses the memory, the data and the memory address being associated with the requestor access code,

the memory access control apparatus comprising

a read request acquirer that acquires from the reader the data to be read from the memory and the memory address of the data;

a cache memory monitor that determines whether the memory address acquired by the read request acquirer is stored in the cache memory;

an access code comparator that compares the requester access code associated with the memory address in the cache memory with a second access code that is information to be used by the reader to access the memory, when the cache memory monitor determines that the memory address is stored in the cache memory; and

an output unit that outputs the data associated with the memory address in the cache memory to the reader, when the requester access code matches the second access code.

28. A memory access control method, comprising:

acquiring data to be read from a memory and a memory address at which the data is to be read, the data and the memory address being acquired from a reader that requests the reading of the data from the memory;

determining whether the memory address acquired is stored in a cache memory that stores data, a memory address of the data, and a requestor access code in association with one another, the data being requested to be written into the memory by a writer that requests writing of the data into the memory or being requested to be read from the memory by the reader, the requester access code being information to be used when a writer or a reader that has a right of access to the data accesses the memory;

comparing the requester access code, which is associated with the memory address in the cache memory, with a second access code that is information to be used by the reader to access the memory, when the memory address is stored in the cache memory; and

outputting the data associated with the memory address in the cache memory to the reader, when the requestor access code matches the second access code.