SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20070138547A1
• Filed: 12/08/2006
• Published: 06/21/2007
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Kazutoshi
• Granted Patent: US 7,719,053 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device comprises a semiconductor region of the first conduction type. A first main electrode is connected to the semiconductor region. A base region of the second conduction type is formed on the semiconductor region. A diffused region of the first conduction type is formed on the base region. A second main electrode is connected to the diffused region and the base region. A first trench is formed extending from a surface of the diffused region to the semiconductor region. A second trench is formed from the first trench deeper than the first trench. A gate electrode is formed on a side of the first trench via a first insulator film. A protruded electrode is formed in the second trench via a second insulator film as protruded lower than the gate electrode.

Claims

1. A semiconductor device, comprising:

a semiconductor region of the first conduction type;

a first main electrode connected to said semiconductor region;

a base region of the second conduction type formed on said semiconductor region;

a diffused region of the first conduction type formed on said base region;

a second main electrode connected to said diffused region and said base region;

a first trench formed extending from a surface of said diffused region to said semiconductor region;

a second trench formed from said first trench much deeper than said first trench;

a gate electrode formed on a side of said first trench via a first insulator film; and

a protruded electrode formed in said second trench via a second insulator film as protruded downward lower than said gate electrode.

2. The semiconductor device according to claim 1, wherein said second insulator film is formed thicker than said first insulator film.

3. The semiconductor device according to claim 1, wherein said protruded electrode is connected to said second main electrode.

4. The semiconductor device according to claim 1, wherein said protruded electrode is connected to said gate electrode.

5. The semiconductor device according to claim 1, wherein said protruded electrode is formed only at a position deeper than a region in depth where said gate electrode is formed.

6. The semiconductor device according to claim 1, wherein top of said protruded electrode is formed at a position deeper than top of said gate electrode.

7. The semiconductor device according to claim 1, further comprising a resistance reduction layer of the first conduction type formed in said semiconductor region adjacent to said second trench and having an impurity concentration higher than that in said semiconductor region.

8. The semiconductor device according to claim 1, wherein said protruded electrode has a cross-sectional area perpendicular to the direction of current flowing in a channel, said cross-sectional area formed smaller than said gate electrode.

9. The semiconductor device according to claim 1, wherein said gate electrode and said protruded electrode are composed of polysilicon.

10. The semiconductor device according to claim 1, wherein said semiconductor device is a MOSFET.

11. The semiconductor device according to claim 1, wherein said semiconductor device is an IGBT.

12. A method of manufacturing a semiconductor device, comprising:

forming on a semiconductor region of the first conduction type a base region of the second conduction type;

forming a first trench through said base region to a depth reaching said semiconductor region;

thermally oxidizing the entire surfaces of said first trench and said base region to form an insulator film;

depositing a conductive film over a surface of said insulator film;

anisotropically etching said conductive film to leave said conductive film only on a side of said first trench;

forming a second trench in a central region at the bottom of said first trench, said second trench extending much deeper than said first trench;

thermally oxidizing the surfaces of said conductive film left after said anisotropic etching and said second trench to form an insulator film; and

depositing a conductive film over a surface of said insulator film formed in said second trench.

13. The method of manufacturing a semiconductor device according to claim 12, wherein said base region of the second conduction type is formed by implanting ions of an impurity of the second conduction type into said semiconductor region of the first conduction type, and then thermally diffusing said implanted impurity of the second conduction type.

14. The method of manufacturing a semiconductor device according to claim 12, wherein said first trench is formed through a process of photolithography or etching.

15. The method of manufacturing a semiconductor device according to claim 12, wherein said second trench is formed to reach a low concentration region having a low impurity concentration in said semiconductor region and not to reach a high concentration region having a high impurity concentration in said semiconductor region.

16. The method of manufacturing a semiconductor device according to claim 12, wherein said conductive layer is formed by depositing polysilicon through a process of CVD.