Formation of raised source/drain structures in NFET with embedded SiGe in PFET

• US 20070138570A1
• Filed: 12/16/2005
• Published: 06/21/2007
• Est. Priority Date: 12/16/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Inventors: Luo, Zhijiong, Holt, Judson, Chong, Yung, Kim, Joo
• Granted Patent: US 7,718,500 B2
• Time in Patent Office: Days
• US Class Current: 257/371
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

Claims

1. A method for forming a semiconductor device comprising the steps of:

a) providing a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region;

b) providing NFET SDE regions adjacent to said NFET gate; and

providing PFET SDE regions adjacent to said PFET gate;

c) forming recesses in said PFET region in the substrate adjacent to said PFET second spacers;

d) forming a PFET embedded Source/drain stressor in the recesses;

e) forming a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded Source/drain stressor;

f) performing a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D epitaxial Si layer to form the raised NFET source/drains.

2. The method of claim 1 wherein

said NFET gate structure is comprised of a NFET gate dielectric, a NFET gate, NFET gate cap comprised of nitride, NFET first spacers, NFET second spacers;

said PFET gate structure is comprised of a PFET gate dielectric, a PFET gate, PFET gate cap comprised of nitride, PFET first spacers, and PFET second spacers and

providing isolation regions between said PFET region and said NFET region.

3. The method of claim 1 wherein the step of:

forming recesses further includes;

forming a dielectric layer over the NFET region;

forming the recesses in the PFET region;

removing the dielectric layer.

4. The method of claim 1 wherein the NFET S/D epitaxial Si layer is between 5% and 20% thicker than the PFET S/D Si epitaxial layer.

5. The method of claim 1 wherein after the NFET S/D epitaxial layer is formed, further comprises:

etching and removing the PFET cap and the NFET cap and removing said second PFET spacers and said second NFET spacer;

forming reduced second PFET spacers and reduced second NFET spacer.

6. The method of claim 1 wherein

the NFET S/D implant is performed by forming a PFET mask over the PFET region;

 

implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D epitaxial Si layer to form the raised NFET Source/drains;

 

removing the PFET mask.

7. The method of claim 1 which further includes:

forming silicide regions over the NFET SDE regions and the PFET embedded Source/drain stressor.

8. The method of claim 1 which further includes:

forming suicide regions over the NFET SDE regions and the PFET embedded Source/drain stressor;

forming a stressor layer over the substrate and NFET gate structure and PFET gate structure.

9. The method of claim 1 which further includes:

forming the PFET embedded source/drain stressor using an in-situ Boron doped SiGe epitaxy process.

10. A method for forming a semiconductor device comprising the steps of:

a) providing a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region;

(1) said NFET gate structure is comprised of a NFET gate dielectric, a NFET gate, NFET gate cap, NFET first spacers, NFET second spacers;

(2) said PFET gate structure is comprised of a PFET gate dielectric, a PFET gate, PFET gate cap, PFET first spacers, and PFET second spacers;

b) providing NFET SDE regions adjacent to said NFET gate; and

providing PFET SDE regions adjacent to said PFET gate;

c) forming recesses in said PFET region in the substrate adjacent to said PFET second spacers;

d) forming a PFET embedded Source/drain stressor using an in-situ Boron doped SiGe epitaxy process;

e) forming a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor;

(1) the NFET S/D epitaxial Si layer is thicker than the PFET S/D epitaxial Si layer;

f) etching and removing the PFET gate cap and the NFET gate cap and removing said second PFET spacers and said second NFET spacer

g) forming reduced second PFET spacers and reduced second NFET spacers;

h) performing a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D epitaxial Si layer to form the NFET raised Source/drains;

i) forming silicide regions over the NFET raised source/drain regions and the PFET embedded source/drain stressor.

11. The method of claim 10 which further includes:

forming a stressor layer over the substrate and NFET gate structure and PFET gate structure.

12. A semiconductor device comprised of:

a) a NFET gate structure over a NFET region in a substrate and a PFET gate structure over a PFET region in the substrate;

b) NFET SDE regions in said NFET region adjacent to said NFET gate; and

PFET SDE regions adjacent to said PFET gate;

c) recesses in said PFET region in the substrate adjacent to said PFET second spacers;

d) PFET embedded source/drain stressor in the recesses;

the PFET embedded source/drain stressors are comprised of doped SiGe;

e) a NFET S/D epitaxial Si layer over the NFET SDE regions and

f) NFET Source/drains regions adjacent to said NFET gate structure in said NFET region and extending into said NFET SDE regions;

 

whereby raised NFET Source/drains are comprised of the NFET Source/drains regions and the NFET S/D epitaxial Si layer.

13. The semiconductor device of claim 12 which further includes:

silicide regions over the NFET raised source/drain regions and the PFET embedded source/drain stressor.

14. The semiconductor device of claim 12 which further includes:

silicide regions over the NFET raised source/drain regions and the PFET embedded source/drain stressor;

a stressor layer over the substrate and NFET gate structure and PFET gate structure.

15. The semiconductor device of claim 12 which further includes:

said NFET gate structure is comprised of a NFET gate dielectric, a NFET gate, and NFET first spacers and reduced second NFET spacer 51 over the NFET first spacers;

 

said PFET gate structure is comprised of a PFET gate dielectric, a PFET gate, and PFET first spacers and reduced second PFET spacers over the PFET first spacers.