AN ELECTRONICS PACKAGE WITH AN INTEGRATED CIRCUIT DEVICE HAVING POST WAFER FABRICATION INTEGRATED PASSIVE COMPONENTS

• US 20070138572A1
• Filed: 07/11/2006
• Published: 06/21/2007
• Est. Priority Date: 12/15/2005
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lam, Ken
• Granted Patent: US 8,258,599 B2
• Time in Patent Office: Days
• US Class Current: 257/379
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/29007 Layer connector smaller than the underlying bonding area
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An apparatus and a method for producing passive components on an integrated circuit device. The integrtated circuit device has post wafer fabrication integrated passive components situated on the opposite substrate side of the device'"'"'s integrated circuitry. Electrical contact pads of the passive components are configured to be coupled to the electronics package contact pads to complete the electronic package.

Claims

1. An integrated circuit comprising:

a substrate having a front side and a back side, the front side of the substrate having one or more integrated circuit devices fabricated thereon; and

at least one passive component fabricated onto the back side of the substrate, the at least one passive component being comprised of a metal structure formed over the back side of the substrate.

2. The integrated circuit of claim 1 wherein the metal is comprised substantially of copper.

3. The integrated circuit of claim 1 further comprising:

a dielectric material formed over the back side of the substrate; and

a metal seed layer formed between the dielectric material and the metal structure.

4. The integrated circuit of claim 3 wherein the dielectric material is a high-k dielectric.

5. The integrated circuit of claim 3 wherein the metal seed layer is comprised substantially of titanium-tungsten.

6. The integrated circuit of claim 1 further comprising bond pads arranged so as to electrically couple to a package substrate.

7. An electronics package comprising:

a package substrate having a plurality of package substrate bond pads; and

an integrated circuit die having

a substrate having a front side and a back side, the front side of the substrate having one or more integrated circuit devices and a plurality of integrated circuit bond pads fabricated thereon; and

at least one passive component fabricated onto the back side of the substrate, the at least one passive component being comprised of a metal structure having a plurality of passive component bond pads, the metal structure and passive component bond pads being formed over the back side of the substrate, the passive component bond pads arranged to correspond to certain ones of the plurality of package substrate bond pads.

8. The electronics package of claim 7 further comprising:

a plurality of wire bonds coupling ones of the plurality of the integrated circuit bond pads with ones of the plurality of package substrate bond pads; and

an encapsulant formed over the package substrate, the integrated circuit die, and the plurality of wire bonds.

9. A method of forming one or more passive components on a substrate, the method comprising:

forming at least one integrated circuit on a front side of a substrate;

forming a photoresist layer over a back side of the substrate;

patterning and etching the photoresist layer to form one or more passive component structures, and

filling the etched areas of the patterned and etched photoresist with a metal.

10. The method of claim 9 further comprising removing substantially all of the remaining etched and patterned photoresist layer.

11. The method of claim 9 further comprising forming a dielectric layer over the back side of the substrate prior to forming the photoresist layer.

12. The method of claim 11 further comprising selecting the dielectric layer to be comprised of a high-k dielectric material.

13. The method of claim 9 further comprising forming a protective coating over the at least one integrated circuit prior to forming the photoresist layer over the back side of the substrate.

14. The method of claim 9 further comprising forming a metal seed layer over the back side of the substrate prior to forming the photoresist layer.

15. The method of claim 9 further comprising;

forming a dielectric layer over the back side of the substrate; and

forming a metal seed layer over the dielectric layer prior to forming the photoresist layer.